SystemVerilog basics RTL constructs

SystemVerilog basics – RTL constructs, available at $29.99, has an average rating of 4.1, with 6 lectures, based on 54 reviews, and has 797 subscribers.

You will learn about High level introduction to SystemVerilog as a language for both Design and Verification RTL Design constructs in SystemVerilog This course is ideal for individuals who are VLSI Design engineers, professionals doing RTL Design or Students in EE/EC/CS streams with keen interest in VLSI domain or Semiconductor Enthusiasts looking to upgrade their design skills It is particularly useful for VLSI Design engineers, professionals doing RTL Design or Students in EE/EC/CS streams with keen interest in VLSI domain or Semiconductor Enthusiasts looking to upgrade their design skills.

Enroll now: SystemVerilog basics – RTL constructs

Summary

Title: SystemVerilog basics – RTL constructs

Price: $29.99

Average Rating: 4.1

Number of Lectures: 6

Number of Published Lectures: 6

Number of Curriculum Items: 6

Number of Published Curriculum Objects: 6

Original Price: $19.99

Quality Status: approved

Status: Live

What You Will Learn

High level introduction to SystemVerilog as a language for both Design and Verification

RTL Design constructs in SystemVerilog

Who Should Attend

VLSI Design engineers, professionals doing RTL Design

Students in EE/EC/CS streams with keen interest in VLSI domain

Semiconductor Enthusiasts looking to upgrade their design skills

Target Audiences

VLSI Design engineers, professionals doing RTL Design

Students in EE/EC/CS streams with keen interest in VLSI domain

Semiconductor Enthusiasts looking to upgrade their design skills

SystemVerilogis a major extension to Verilog-2001, adding significant new features to Verilog for design, assertions, synthesis and verification. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of a complete Object-Oriented paradigm features. There are also considerable improvements in the usability of Verilog for RTL design.

In this course we cover the basics of IEEE 1800 – SystemVerilog. Topics covered will be useful for both RTL designers and verification engineers as it covers the basics. As a basic course this does not go in-depth into Synthesis related details, that shall be covered in an advanced course later.

Objectives

To explore the new features of SystemVerilog for RTL design and demonstrate the improvements in modeling with SV

Also introduce audience to new complex aggregate data types that assist in advanced scoreboards, reference models etc. for verification and modeling.

Prerequisites

Attendees must be familiar with Verilog and ideally, but not essentially, Verilog-2001. No prior knowledge of SystemVerilog is required. Digital design fundamentals is a must pre-requisite.

Following topics are covered:

1. Introduction to SystemVerilog

Language evolution

SV Design

SV Assertions

SV testbench

DPI

API

2. Introduction to SystemVerilog

2.Data types, procedural constructs – enhancements

Data types, type checking, type cast

Enhanced always, case/if else, loop, flow

3. Aggregate data types – arrays

Enhancements to static/fixed Arrays from Verilog-2001

Multi-dimensional arrays, system functions

Dynamic arrays

Associative arrays

Queues

Array query operators

4. Packages, port connections

Packages

Enhanced port connection styles

5. Interfaces in SystemVerilog

Interface – Grouping signals

Modport

Clocking block

Course Curriculum

Chapter 1: Introduction to SystemVerilog

Lecture 1: Introduction to SystemVerilog

Chapter 2: Data Types, procedural constructs – enhancements

Lecture 1: Data Types, procedural constructs – enhancements

Chapter 3: Arrays – static arrays in SystemVerilog

Lecture 1: Arrays – static arrays in SystemVerilog

Chapter 4: Dynamic arrays, Associative arrays, Queues and array methods

Lecture 1: Dynamic arrays, Associative arrays, Queues and array methods

Chapter 5: Packages, Port connections

Lecture 1: Packages, Port connections

Chapter 6: Interfaces in SystemVerilog

Lecture 1: Interfaces in SystemVerilog

Instructors

Srinivasan Venkataramanan
CTO at CVC Pvt Ltd

Rating Distribution

1 stars: 6 votes

2 stars: 3 votes

3 stars: 13 votes

4 stars: 16 votes

5 stars: 16 votes

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