Xilinx Vivado Essentials for the Logic Designer

Xilinx Vivado Essentials for the Logic Designer, available at $44.99, has an average rating of 4.68, with 8 lectures, based on 83 reviews, and has 672 subscribers.

You will learn about Getting started designing FPGAs with Xilinx Vivado Design Tools This course is ideal for individuals who are Beginning Xilinx FPGA Logic Designers It is particularly useful for Beginning Xilinx FPGA Logic Designers.

Enroll now: Xilinx Vivado Essentials for the Logic Designer

Summary

Title: Xilinx Vivado Essentials for the Logic Designer

Price: $44.99

Average Rating: 4.68

Number of Lectures: 8

Number of Published Lectures: 8

Number of Curriculum Items: 8

Number of Published Curriculum Objects: 8

Original Price: $19.99

Quality Status: approved

Status: Live

What You Will Learn

Who Should Attend

Target Audiences

Xilinx Vivado can be overwhelming for a logic designer who is creating their first design for a contemporary Xilinx device.   This course describes the various design flows, including hdl only flow, block flow and a hybrid of block and hdl.  Each flow includes a simulation options, and adding the Integrated Logic Analyzer to a design.  We introduce the Vitis SDK to allow the logic designer to create simple test programs, and describe the AXI4-Lite bus which is the most common interface between processor and logic.

Course Curriculum

Chapter 1: Introduction

Lecture 1: Introduction

Chapter 2: Vivado HDL Design with VHDL or Verilog

Lecture 1: Vivado HDL Design

Chapter 3: Vivado Block Diagram

Lecture 1: Vivado Block Diagram

Chapter 4: Vivado Hybrid Block Diagram / HDL Design

Lecture 1: Vivado hybrid design

Chapter 5: Vivado Integrated Logic Analyzer

Lecture 1: Using a Xilinx Vivado Integrated Logic Analyzer

Chapter 6: Vivado SDK

Lecture 1: Vivado SDK

Chapter 7: Processor / HDL Interface with AXI Bus and GPIOs

Lecture 1: AXI4-Lite and GPIO for processor Interface

Chapter 8: Processor Interrupts from HDL

Lecture 1: Utilizing interrupts to the processor in Vivado and SDK

Instructors

Scott Dickson
FPGA / ASIC Design Engineer

Rating Distribution

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