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VSDOpen2020 VLSI online conference

  • DESIGN
  • Jan 01, 2025
SynopsisVSDOpen2020 – VLSI online conference, available at $44....
VSDOpen2020 VLSI online conference  No.1

VSDOpen2020 – VLSI online conference, available at $44.99, has an average rating of 4.45, with 36 lectures, based on 12 reviews, and has 1802 subscribers.

You will learn about How students from all over world designed analog IPs and RISC-V core from scratch Launch of VSD-Intelligent Assessment Technology and its benefits in VLSI training Applying community models to ICs – Why and How? RISC-V and open source hardware – A golden opportunity for India semiconductor industry Computation in the Post-Moore Era: Reflecting on the The role of Open Source A brief history of open hardware: learning from the freeand open source software movement Government Initiatives in ESDM Space This course is ideal for individuals who are Anyone who wants to get an overview of VLSI industry and get started in the field of open-source or Anyone who wants to learn how to build analog IPs from scratch or Anyone who wants to know about next-gen cloud based RISC-V and VLSI trainings at affordable costs It is particularly useful for Anyone who wants to get an overview of VLSI industry and get started in the field of open-source or Anyone who wants to learn how to build analog IPs from scratch or Anyone who wants to know about next-gen cloud based RISC-V and VLSI trainings at affordable costs.

Enroll now: VSDOpen2020 – VLSI online conference

Summary

Title: VSDOpen2020 – VLSI online conference

Price: $44.99

Average Rating: 4.45

Number of Lectures: 36

Number of Published Lectures: 36

Number of Curriculum Items: 36

Number of Published Curriculum Objects: 36

Original Price: $89.99

Quality Status: approved

Status: Live

What You Will Learn

  • How students from all over world designed analog IPs and RISC-V core from scratch
  • Launch of VSD-Intelligent Assessment Technology and its benefits in VLSI training
  • Applying community models to ICs – Why and How?
  • RISC-V and open source hardware – A golden opportunity for India semiconductor industry
  • Computation in the Post-Moore Era: Reflecting on the The role of Open Source
  • A brief history of open hardware: learning from the freeand open source software movement
  • Government Initiatives in ESDM Space
  • Who Should Attend

  • Anyone who wants to get an overview of VLSI industry and get started in the field of open-source
  • Anyone who wants to learn how to build analog IPs from scratch
  • Anyone who wants to know about next-gen cloud based RISC-V and VLSI trainings at affordable costs
  • Target Audiences

  • Anyone who wants to get an overview of VLSI industry and get started in the field of open-source
  • Anyone who wants to learn how to build analog IPs from scratch
  • Anyone who wants to know about next-gen cloud based RISC-V and VLSI trainings at affordable costs
  • JOIN VSDOpen2020 and be a part of open-source revolution !!

    VSDOpen 2020 was bigger and better !!

    VSDOpen 2020 had LIVE Tutorial Session for first 3 days

    VSDOpen 2020 showcased open-source analog IP’s

    VSDOpen 2020 was for 4-days

    View VSDOpen2020 last day conference!!

    We are excited to showcase some masterpieces of work done by Research Interns over last year, and also, we are really excited to introduce you to novel techniques of learning and designing analog/digital IP’s. This time, we are about to showcase you a list of projects which was achieved for the very first time in the field of open-source.

    To Begin with: First time in the open-source world,

    1. We have open-source analog IPs built from scratch using OSU-180nm PDK, Magic and eSim EDA tools, by undergrad and post-grad students. Unbelievable!!

    2. We displayed to the RISC-V community around the globe how you can design a basic RISC-V core in just 5-days from scratch using TL-Verilog and Makerchip IDE. Unbelievable!!

    3. We released a cloud-based VSD-Intelligent Assessment Technology platform which enables VLSI training for all time-zones at one go and is about 99% effective compared to any other training around the globe.

    4. We will show you how you can develop your own SoC using real 130nm PDK from Skywaterand OpenLANE EDAtool-chain from efabless

    Course Curriculum

    Chapter 1: Introduction

    Lecture 1: Welcome to VSDOpen2020

    Lecture 2: VSDOpen2020 conference agenda

    Chapter 2: Applying Community Models to ICs: Why and How – By Mike Wishart

    Lecture 1: Applying community models to ICs – Part 1

    Lecture 2: Applying community models to ICs – Part 2

    Lecture 3: Applying community models to ICs – Part 3

    Lecture 4: Applying community models to ICs – Part 4

    Chapter 3: Open Source IP Designer track – Internship on SRAM

    Lecture 1: SRAM (32kbits or 4kB), 1.8V and access time is <2.5ns – Part 1

    Lecture 2: SRAM (32kbits or 4kB), 1.8V and access time is <2.5ns – Part 2

    Chapter 4: Open Source IP Designer track – Effective RISC-V and VLSI trainings on VSD-IAT

    Lecture 1: Next Gen open-source VLSI/RISC-V trainings on VSD-IAT and Makerchip – Part 1

    Lecture 2: Next Gen open-source VLSI/RISC-V trainings on VSD-IAT and Makerchip – Part 2

    Lecture 3: VSD-IAT workshops promotional video

    Chapter 5: RISC-V and opensource HW – A golden opportunity for India semiconductor industry

    Lecture 1: RISC-V and open source hardware – Part 1

    Lecture 2: RISC-V and open source hardware – Part 2

    Lecture 3: RISC-V and open source hardware – Part 3

    Chapter 6: Open Source IP Designer track – Internship on 10-bit potentiometric DAC

    Lecture 1: 10-bit potentiometric DAC – Part 1

    Lecture 2: 10-bit potentiometric DAC – Part 2

    Chapter 7: Open Source IP Designer track – Internship on PLL

    Lecture 1: On-chip Clock multiplier (pll) (In 5MHz – 12Mhz, Out 40MHz – 100MHz) – Part 1

    Lecture 2: On-chip Clock multiplier (pll) (In 5MHz – 12Mhz, Out 40MHz – 100MHz) – Part 2

    Lecture 3: On-chip Clock multiplier (pll) (In 5MHz – 12Mhz, Out 40MHz – 100MHz) – Part 3

    Chapter 8: Computation in the Post-Moore Era: Reflecting on the The role of Open Source

    Lecture 1: Computation in Post-Moore Era: Reflecting on the role of Open Source – Part 1

    Lecture 2: Computation in Post-Moore Era: Reflecting on the role of Open Source – Part 2

    Lecture 3: Computation in Post-Moore Era: Reflecting on the role of Open Source – Part 3

    Lecture 4: Computation in Post-Moore Era: Reflecting on the role of Open Source – Part 4

    Chapter 9: A brief history of open hardware: Learning from the free & open source software

    Lecture 1: Brief history of open HW: Learning from free & opensource SW – Part 1

    Lecture 2: Brief history of open HW: Learning from free & opensource SW – Part 2

    Lecture 3: Brief history of open HW: Learning from free & opensource SW – Part 3

    Lecture 4: Brief history of open HW: Learning from free & opensource SW – Part 4

    Chapter 10: Open Source IP Designer track – Internship on 10-bit ADC

    Lecture 1: 10-bit ADC – Part 1

    Lecture 2: 10-bit ADC – Part 2

    Lecture 3: 10-bit ADC – Part 3

    Chapter 11: Indian Government Initiatives in ESDM Space

    Lecture 1: Government Initiatives in ESDM Space – Part 1

    Lecture 2: Government Initiatives in ESDM Space – Part 2

    Lecture 3: Government Initiatives in ESDM Space – Part 3

    Lecture 4: Government Initiatives in ESDM Space – Part 4

    Lecture 5: Government Initiatives in ESDM Space – Part 5

    Chapter 12: Conclusion

    Lecture 1: VSDOpen2020 Final Thoughts – Future path of Open source and VSD

    Instructors

  • VSDOpen2020 VLSI online conference  No.2
    Kunal Ghosh
    Digital and Sign-off expert at VLSI System Design(VSD)
  • Rating Distribution

  • 1 stars: 1 votes
  • 2 stars: 1 votes
  • 3 stars: 0 votes
  • 4 stars: 4 votes
  • 5 stars: 6 votes
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