VSD Static Timing Analysis I

VSD – Static Timing Analysis – I, available at $59.99, has an average rating of 4.26, with 28 lectures, based on 2589 reviews, and has 7157 subscribers.

You will learn about Understand various STA checks for timing closure Able to do a quality analysis for real designs Know-how on how real STA works in industries, something which you will not find in any books Step-by-step and structured timing analysis This course is ideal for individuals who are Course starts from basic timing path to advanced latch checks, so basics of flipflops should be enough It is particularly useful for Course starts from basic timing path to advanced latch checks, so basics of flipflops should be enough.

Enroll now: VSD – Static Timing Analysis – I

Summary

Title: VSD – Static Timing Analysis – I

Price: $59.99

Average Rating: 4.26

Number of Lectures: 28

Number of Published Lectures: 28

Number of Curriculum Items: 28

Number of Published Curriculum Objects: 28

Original Price: $84.99

Quality Status: approved

Status: Live

What You Will Learn

Understand various STA checks for timing closure

Able to do a quality analysis for real designs

Know-how on how real STA works in industries, something which you will not find in any books

Step-by-step and structured timing analysis

Who Should Attend

Course starts from basic timing path to advanced latch checks, so basics of flipflops should be enough

Target Audiences

Course starts from basic timing path to advanced latch checks, so basics of flipflops should be enough

Static timing analysis comprises broadly for timing checks, constraints and library. Having all of them in a single course makes it bulky. So we decided to have it in 3 parts and this is part I – Essential timing checks. This course will give an eagle’s eye to every timing check that is being performed in current industries for sign-off. This will also introduce you to basic terminologies for timing, which are needed for advanced courses on STA.

Timing comes at every step of physical design flow, but in this course, we primarily focus on signoff timing i.e. looking into each and every corner of design for any timing violations

The course starts from very basic and gradually takes you to an advanced level at an intermediate pace. So no questions on you missing any details

Hope you enjoy learning this course in the same way we enjoyed making them.

Happy Learning !!

Course Curriculum

Chapter 1: Introduction and agenda

Lecture 1: Introduction

Lecture 2: Introduction to timing path and arrival time

Lecture 3: Introduction to required time and slack

Lecture 4: Introduction to basic categories of setup and hold analysis

Lecture 5: Introduction to data check and latch timing

Lecture 6: Introduction to slew, load and clock checks

Chapter 2: First things first – Introduction to timing graph

Lecture 1: Convert logic gates into nodes

Lecture 2: Compute actual arrival time (AAT)

Lecture 3: Compute required arrival time (RAT)

Lecture 4: Compute slack and introduction to GBA-PBA analysis

Lecture 5: Convert pins to nodes and compute AAT, RAT and slack

Chapter 3: Clk-to-q delay, library setup, hold time and jitter

Lecture 1: Introduction to transistor level circuit for flops

Lecture 2: Negative and positive latch transistor level operation

Lecture 3: Library setup time calculation

Lecture 4: Clk-q delay calculation

Lecture 5: Steps to create eye diagram for jitter analysis

Lecture 6: Jitter extraction and accounting in setup timing analysis

Chapter 4: Textual timing reports and hold analysis

Lecture 1: Setup analysis – graphical to textual representation

Lecture 2: Hold analysis with real clocks

Lecture 3: Hold analysis – graphical to textual representation

Chapter 5: On-chip variation

Lecture 1: Sources of variation – etching

Lecture 2: Sources of variation – oxide thickness

Lecture 3: Relationship between resistance, drain current and delay

Chapter 6: OCV timing and pessimism removal

Lecture 1: OCV based setup timing analysis

Lecture 2: Setup timing analysis after pessimism removal

Lecture 3: OCV based hold timing analysis

Lecture 4: Hold timing analysis after pessimism removal

Chapter 7: Conclusion

Lecture 1: Conclusion and next topics!!

Instructors

Kunal Ghosh
Digital and Sign-off expert at VLSI System Design(VSD)

Rating Distribution

1 stars: 31 votes

2 stars: 55 votes

3 stars: 372 votes

4 stars: 1053 votes

5 stars: 1078 votes

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