VSD TCL programming From novice to expert Part 1
- Development
- Apr 15, 2025

VSD – TCL programming – From novice to expert – Part 1, available at $44.99, has an average rating of 4.35, with 29 lectures, based on 625 reviews, and has 3596 subscribers.
You will learn about Build TCL scripts on their own from scratch Build their own UI (user-interface) Build their own procs and commands This course is ideal for individuals who are Anyone who wants to do TCL programming or Anyone who wants to learn basic programming algorithm and data flow or Anyone who wants to code It is particularly useful for Anyone who wants to do TCL programming or Anyone who wants to learn basic programming algorithm and data flow or Anyone who wants to code.
Enroll now: VSD – TCL programming – From novice to expert – Part 1
Summary
Title: VSD – TCL programming – From novice to expert – Part 1
Price: $44.99
Average Rating: 4.35
Number of Lectures: 29
Number of Published Lectures: 29
Number of Curriculum Items: 29
Number of Published Curriculum Objects: 29
Original Price: $84.99
Quality Status: approved
Status: Live
What You Will Learn
Who Should Attend
Target Audiences
And I really believe in that
I was a novice in TCL programming 10 years back. One thing that led from novice to an expert is “Practice”
Be it learning scripting language or an EDA tool, nothing beats ‘concepts’. I have been proving this in my courses, how learning a tool is the last 5% task of entire learning flow.
My students, who have been working with on several projects and also learning through my courses, have not only learned semiconductors, but lived the journey. And I promise, the same will happen with my this course on TCL scripting as well.
I have been using the same approach in last 10 years for solving problems, be it a TCL script issue or an issue with STA timing violation or an issue with DRC or an issue with floor planning or an issue with routing congestion, you name it..
You will witness the same in all my courses and in this one as well. Let’s unveil the concepts of data flow and manipulation using TCL scripts
Course Curriculum
Chapter 1: Introduction
Lecture 1: Introduction to TCL task
Lecture 2: Introduction to sub-task
Chapter 2: Sub-Task One : VSDSYNTH Toolbox usage scenarios
Lecture 1: Scenario 1 – User doesnt provides input csv file
Lecture 2: Scenario 2 & 3 – User providing incorrect csv OR typing -help
Chapter 3: Sub-Task Two – From CSV to format[1] and SDC – Variable Creation
Lecture 1: Various tasks involved in format conversion
Lecture 2: openMSP430_design_details.csv
Lecture 3: Auto-Create variables using matrix and arrays
Lecture 4: Initialize variables for auto-creation variables task
Lecture 5: Auto creation of first variable – DesignName
Lecture 6: Auto creation of variables complete
Lecture 7: Variable Creation DEMO using TCL
Chapter 4: Sub-Task Two – From CSV to format[1] and SDC – Processing constraints,csv
Lecture 1: Checking existence of files and folders mentioned in design_details.csv
Lecture 2: Convert constraints.csv file to a matrix object
Lecture 3: Compute row number using complex matrix proccessing
Lecture 4: DEMO for computing row numbers
Chapter 5: Sub-Task Two – From CSV to format[1] and SDC – Processing clock constraints
Lecture 1: Algorithm to identify column number for clock latency constraints
Lecture 2: Start writing clock latency constraints in SDC file
Lecture 3: Complete clock latency constraints and clock slew constraints in SDC file
Lecture 4: Code to create clock constraints with clock period and duty cycle
Lecture 5: DEMO for creating complete clock constraints
Chapter 6: Sub-Task Two – From CSV to format[1] and SDC – Processing input constraints
Lecture 1: Introduction to task of differentiating between bits and bus
Lecture 2: Algorithm to categorize input ports as bits and bussed
Lecture 3: File access and pattern creation steps
Lecture 4: Regular expression and regular substitute to get fixed space strings
Lecture 5: Demo for grepping input ports from all verilogs and reformatting for fixed space
Lecture 6: Read, split, uniquify, sort and join input ports to remove duplication
Lecture 7: Evaluate length of string and Demo of bits/bussed differentiation script
Lecture 8: Demo for input constraints generation and bits/bussed differentiation
Chapter 7: Full script for download and Conclusion
Lecture 1: Constraints generation logic for output port and Conclusion!!
Instructors

Kunal Ghosh
Digital and Sign-off expert at VLSI System Design(VSD)
Rating Distribution
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