VSD Intern OpenRAM configuration for 4kB SRAM using Sky130

VSD Intern – OpenRAM configuration for 4kB SRAM using Sky130, available at $44.99, has an average rating of 3.75, with 16 lectures, based on 21 reviews, and has 212 subscribers.

You will learn about Configure open-source memory compiler OpenRAM for any memory size SRAM custom cell design Memory GDS/Lib/Lef file types This course is ideal for individuals who are VLSI Beginner who wants to quickly learn about various custom cells like 6T-SRAM, DFF or VLSI professionals who want to know how to configure open-source memory compiler OpenRAM for custom memory IP generation It is particularly useful for VLSI Beginner who wants to quickly learn about various custom cells like 6T-SRAM, DFF or VLSI professionals who want to know how to configure open-source memory compiler OpenRAM for custom memory IP generation.

Enroll now: VSD Intern – OpenRAM configuration for 4kB SRAM using Sky130

Summary

Title: VSD Intern – OpenRAM configuration for 4kB SRAM using Sky130

Price: $44.99

Average Rating: 3.75

Number of Lectures: 16

Number of Published Lectures: 16

Number of Curriculum Items: 16

Number of Published Curriculum Objects: 16

Original Price: $89.99

Quality Status: approved

Status: Live

What You Will Learn

Configure open-source memory compiler OpenRAM for any memory size

SRAM custom cell design

Memory GDS/Lib/Lef file types

Who Should Attend

VLSI Beginner who wants to quickly learn about various custom cells like 6T-SRAM, DFF

VLSI professionals who want to know how to configure open-source memory compiler OpenRAM for custom memory IP generation

Target Audiences

VLSI Beginner who wants to quickly learn about various custom cells like 6T-SRAM, DFF

VLSI professionals who want to know how to configure open-source memory compiler OpenRAM for custom memory IP generation

This webinar aims at design of 1024×32 SRAM cell array (32Kbits or 4KB) with a configuration of 1.8 V operating voltage and access time less than 2.5ns using Google SkyWater SKY130 PDKs and OpenRAM memory compiler.

Static Random-Access Memory (SRAM) has become a standard element of any Application Specific Integrated Circuit (ASIC), System-On-Chip (SoC), or other micro-architectures. For this wide variety of applications, SRAMs are configured using parameters like the word-length, bit lines, operating voltage, access time, and most importantly the technology node. The access time of an SRAM cell is the time require for a read or write operation of SRAM.

Manually configuring the SRAM for every change in parameter seems a slightly in-efficient and tedious task. Due to this reason, the memory compiler is used on a large scale, as it facilitates easy configuration and optimization of memory. OpenRAM, an open-source memory compiler is used for characterization and generation of SRAM designs.

This webinar mentioned multiple open-source circuit schematic design, layout design, SPICE simulations tools and memory compiler. The tools used are explained in detail. All the Skywater SKY130 PDKs related files are added to the repository mentioned in webinar, which can be used without installing the complete PDKs. To install or get other details of Skywater PDKs, it can be found in Skywater official website

Course Curriculum

Chapter 1: Introduction

Lecture 1: Introduction to OpenRAM

Lecture 2: Reasons to use OpenRAM and Sky130 technology

Chapter 2: Environment Setup and custom cells description

Lecture 1: OpenRAM environment setup

Lecture 2: Bit-cells and sense amplifier details

Lecture 3: Dummy & replica bit cells, D-flipflop and write driver details

Chapter 3: OpenRAM technology setup

Lecture 1: OpenRAM directory structure

Lecture 2: GDS file creation

Lecture 3: Tech file setup

Lecture 4: Interconnect stack layer name and technology parameters

Lecture 5: DRC rules and SPICE technology setup

Chapter 4: Steps to execute OpenRAM

Lecture 1: OpenRAM configuration script

Lecture 2: Execute and review OpenRAM output files

Chapter 5: Challenges, issues and fixes

Lecture 1: Custom cells boundry box

Lecture 2: GDS pins and tech layers

Lecture 3: GDS DRC issues

Chapter 6: Conclusion

Lecture 1: Summary and conclusion

Instructors

Kunal Ghosh
Digital and Sign-off expert at VLSI System Design(VSD)

Shon Taware
VLSI Design Enthusiast

Rating Distribution

1 stars: 1 votes

2 stars: 0 votes

3 stars: 5 votes

4 stars: 10 votes

5 stars: 5 votes

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