VSD Intern Analog Comparator Design using Sky130

VSD Intern – Analog Comparator Design using Sky130, available at $27.99, has an average rating of 3.55, with 15 lectures, based on 12 reviews, and has 144 subscribers.

You will learn about Basics of Analog comparator Circuit design and layout Integrate Sky130 foundry PDKs with comparator circuit design Basics of comparator hysteresis characteristics This course is ideal for individuals who are Beginner who is curious to know about circuit design and layout or Physical Design Professionals curious to know about IP design It is particularly useful for Beginner who is curious to know about circuit design and layout or Physical Design Professionals curious to know about IP design.

Enroll now: VSD Intern – Analog Comparator Design using Sky130

Summary

Title: VSD Intern – Analog Comparator Design using Sky130

Price: $27.99

Average Rating: 3.55

Number of Lectures: 15

Number of Published Lectures: 15

Number of Curriculum Items: 15

Number of Published Curriculum Objects: 15

Original Price: $199.99

Quality Status: approved

Status: Live

What You Will Learn

Basics of Analog comparator Circuit design and layout

Integrate Sky130 foundry PDKs with comparator circuit design

Basics of comparator hysteresis characteristics

Who Should Attend

Beginner who is curious to know about circuit design and layout

Physical Design Professionals curious to know about IP design

Target Audiences

Beginner who is curious to know about circuit design and layout

Physical Design Professionals curious to know about IP design

A comparator is a device that compares two analog inputs and outputs a digital signal indicating which input is larger. So it has two analog input terminals and one binary digital output. When the difference between two analog input signals approach zero, noise on the inputs will cause spurious switching of digital output. This rapid change in output due to noise can be prevented by hysteresis. Hysteresis is switching the output high or low at different input signal levels. In place of one switching point, hysteresis introduces two: one for rising edge, and one for falling edge of voltage or current. The difference between the higher-level trip value (VH) and the lower-level trip value (VL) equals the hysteresis voltage (HYST).

A comparator can be divided into three distinctive pieces – a front-end differential amplifier, amplifier stage and output stage.

This comparator consists of

1. Front-end differential amplifier

2. Amplifier of the output from front-end differential sage

3. NAND gate to act as buffer as well as incorporate the enable pin

4. Inverter to act as final buffer before output. The NAND and Inverter improves the slew and provides a little gain.

5. Positive feedback differential set-up.

Various Comparator specifications are listed below:

Propagation Delay -The time difference between the input crossing the reference voltage and the output changing the logic state. Generally, comparators are fast

Input Offset -The difference between the input voltages at the instance where output voltage equals zero volts

Gain–Ideal Comparator has infinite gain and output jumps from low to high at a specific difference in input voltage. Ideal comparators will have a linear transfer curve.

There are multiple other parameters like output swing, Output type, input and output current and impedance but we will focus on above including hysteresis.

This webinar will discuss all design, layout and specification details using ngspice, Xschem and Magic

Course Curriculum

Chapter 1: Introduction

Lecture 1: Introduction

Chapter 2: Tool Installation And Testing (LIVE Labs)

Lecture 1: Steps to install MAGIC

Lecture 2: Steps to install Sky130 PDK and NGSpice

Lecture 3: Steps to configure Xschem with Sky130 PDK

Lecture 4: Final Steps to patch Sky130 PDK with NGSpice and Xschem

Lecture 5: Xschem testing with Sky130 PDKs

Chapter 3: Comparator Circuit design and layout (LIVE Labs)

Lecture 1: Introduction To Comparator Circuit Components And Pre-layout Simulations

Lecture 2: Hysteresis And Simulation Stimulus

Lecture 3: Review EN, INP and IHyst Inputs

Lecture 4: Review Differential Stage Output – Vdiff

Lecture 5: Review Amplifier Output

Lecture 6: Impact Of Changing Differential Voltage On Common Mode

Lecture 7: Circuit To Layout Mapping

Lecture 8: Transistor Selection And Tech File Details

Chapter 4: Conclusion

Lecture 1: Post-Layout Simulation, Issues And FutureWork

Instructors

Kunal Ghosh
Digital and Sign-off expert at VLSI System Design(VSD)

Malay Das
Software Engineer and Analog Layout and VLSI Design Engineer

Rating Distribution

1 stars: 2 votes

2 stars: 0 votes

3 stars: 4 votes

4 stars: 3 votes

5 stars: 3 votes

Frequently Asked Questions

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You can view and review the lecture materials indefinitely, like an on-demand channel.

Can I take my courses with me wherever I go?

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