Learn VHDL, ISE and FPGA by Designing a basic Home Alarm

Learn VHDL, ISE and FPGA by Designing a basic Home Alarm, available at $19.99, has an average rating of 4.1, with 58 lectures, 4 quizzes, based on 76 reviews, and has 647 subscribers.

You will learn about Write VHDL Codes Use FPGA Editor to understand a design and the available resources Create Testbenches and Run Simulation Create Timing Constraints Run Timing Analysis Add constraints with PlanAhead View and understand the Technology Schematics after Synthesis Generate an IP Core Run Implementation Extract information from ISE Reports Solve errors and understand warnings encountered in the ISE flow Configure the FPGA and ROM with iMPACT This course is ideal for individuals who are The course was designed to help you get started from the basics and rise to an intermediate level or Students or Professionals who want to gain these skills or Electronics Enthusiasts or Research Scientists It is particularly useful for The course was designed to help you get started from the basics and rise to an intermediate level or Students or Professionals who want to gain these skills or Electronics Enthusiasts or Research Scientists.

Enroll now: Learn VHDL, ISE and FPGA by Designing a basic Home Alarm

Summary

Title: Learn VHDL, ISE and FPGA by Designing a basic Home Alarm

Price: $19.99

Average Rating: 4.1

Number of Lectures: 58

Number of Quizzes: 4

Number of Published Lectures: 58

Number of Published Quizzes: 4

Number of Curriculum Items: 62

Number of Published Curriculum Objects: 62

Original Price: 199.99

Quality Status: approved

Status: Live

What You Will Learn

Write VHDL Codes

Use FPGA Editor to understand a design and the available resources

Create Testbenches and Run Simulation

Create Timing Constraints

Run Timing Analysis

Add constraints with PlanAhead

View and understand the Technology Schematics after Synthesis

Generate an IP Core

Run Implementation

Extract information from ISE Reports

Solve errors and understand warnings encountered in the ISE flow

Configure the FPGA and ROM with iMPACT

Who Should Attend

The course was designed to help you get started from the basics and rise to an intermediate level

Students

Professionals who want to gain these skills

Electronics Enthusiasts

Research Scientists

Target Audiences

The course was designed to help you get started from the basics and rise to an intermediate level

Students

Professionals who want to gain these skills

Electronics Enthusiasts

Research Scientists

This course was designed to equip you with the knowledge and skill that will get you up to speed with FPGA Design in VHDL. You will be expected to have some basic knowledge on digital electronics such as the meaning of Flip Flops, Gates and Finite State Machine, and also some basics of programming language would help in the course.

Although the design flow will be dealt with in almost its entirety, the course starts from the basics and take you up to an intermediate level, where you will be able to take a design from a concept through the different stages of design until seeing the design work on a board.

The course is structured in four parts, starting with a simplistic view at how FPGAs work and the resources that are available on a typical FPGA. The tool FPGA Editor will be used. Then an overview of ISE Flow will be presented in part 2, along with demos on how the tool is downloaded, installed and used. The third part of the course will explain and demonstrate how the most useful VHDL syntaxes are written, and at each step, the Technology Schematic is viewed to understand how VHDL codes are synthesized into logic.

The last part is about designing a Home Alarm System from the concept and State Diagram. A step-by-step approach is used to show all the stages of the flow, including writing of the codes, Synthesize, add constraints, run Implementation, Timing Analysis, Behavioural Simulation and Post implementation Simulation and Configurationof the FPGA and PROM on a Basys 2 board.

The course consists of 6 hours of videos, spread over 50 lectures, and provide demos to show how the tool is used effectively.

Course Curriculum

Chapter 1: Overview of the Course

Lecture 1: The Goals

Chapter 2: The Device

Lecture 1: Introduction to FPGAs

Lecture 2: Look Up Tables

Lecture 3: Resources on the FPGA

Lecture 4: Viewing Resources on FPGA Editor

Chapter 3: The Software

Lecture 1: The ISE Flow

Lecture 2: Download and Install ISE Webpack

Lecture 3: Get a License for ISE

Lecture 4: The ISE GUI – Project Navigator

Lecture 5: Launching FPGA Editor

Chapter 4: The Language

Lecture 1: Main parts of VHDL

Lecture 2: Data Types

Lecture 3: Operators

Lecture 4: Synthesize a simple piece of VHDL code

Lecture 5: View RTL and Technology Schematic

Lecture 6: NOT Gate

Lecture 7: AND/OR Gates

Lecture 8: XOR/NOR Gates

Lecture 9: Standard Logic Vector

Lecture 10: A Logic Unit

Lecture 11: Synchronous process

Lecture 12: Synthesis option

Lecture 13: Make a design synchronous

Lecture 14: Language Template and Synthesis of Flip Flop example code

Lecture 15: Block RAM synthesis from Language Template

Lecture 16: Signals, Constants and Variables

Lecture 17: Arrays

Lecture 18: Generics

Lecture 19: Addition and Subtraction

Lecture 20: Multiplication

Lecture 21: Libraries and Packages

Lecture 22: If Statements

Lecture 23: Case Statements

Lecture 24: Loops

Lecture 25: Functions

Chapter 5: An Example

Lecture 1: Overview of the Alarm System

Lecture 2: The State Diagram

Lecture 3: Finite States Machine Template

Lecture 4: Define the States

Lecture 5: Editing the Sync Process

Lecture 6: Editing the Output Process

Lecture 7: Editing the Next State Decode Process

Lecture 8: Running Check Syntax and Debug syntax errors

Lecture 9: Adding alarm output and sensor input

Lecture 10: Add a Debouncer Circuit

Lecture 11: Introduction to Simulation

Lecture 12: Create a Test Bench for Simulation

Lecture 13: Run ISIM Simulation

Lecture 14: Instantiate the Design in a Top Module

Lecture 15: Adding a Digital Clock Manager

Lecture 16: Adding Location Constraints

Lecture 17: Adding Timing Constraints

Lecture 18: Run Implementation

Lecture 19: Run Post Route Simulation

Lecture 20: Timing Analysis

Lecture 21: Generate Programming File

Lecture 22: Load design on Basys 2 Board

Lecture 23: Powerpoint of the course in pdf

Instructors

M Ajmir GOOLAM HOSSEN
Instructor, Technologist, Entrepreneur

Rating Distribution

1 stars: 2 votes

2 stars: 1 votes

3 stars: 18 votes

4 stars: 31 votes

5 stars: 24 votes

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