FPGA Embedded Design, Part 4 Microprocessor Design

FPGA Embedded Design, Part 4 – Microprocessor Design, available at $64.99, has an average rating of 4, with 129 lectures, based on 108 reviews, and has 1267 subscribers.

You will learn about How a CPU works. How to design a CPU core of your own. How to design an Instruction Set Architecture How to design a CPU core in Verilog. How to synthesize a CPU core for Altera and Xilinx FPGAs. This course is ideal for individuals who are Embedded designers who want to dive deeper into Soft-Processor design. or Intermediate FPGA enthusiasts who are curious about CPU design. or Anyone are taking the FPGA Embedded Design series by Closure Labs. It is particularly useful for Embedded designers who want to dive deeper into Soft-Processor design. or Intermediate FPGA enthusiasts who are curious about CPU design. or Anyone are taking the FPGA Embedded Design series by Closure Labs.

Enroll now: FPGA Embedded Design, Part 4 – Microprocessor Design

Summary

Title: FPGA Embedded Design, Part 4 – Microprocessor Design

Price: $64.99

Average Rating: 4

Number of Lectures: 129

Number of Published Lectures: 129

Number of Curriculum Items: 129

Number of Published Curriculum Objects: 129

Original Price: $199.99

Quality Status: approved

Status: Live

What You Will Learn

How a CPU works.

How to design a CPU core of your own.

How to design an Instruction Set Architecture

How to design a CPU core in Verilog.

How to synthesize a CPU core for Altera and Xilinx FPGAs.

Who Should Attend

Embedded designers who want to dive deeper into Soft-Processor design.

Intermediate FPGA enthusiasts who are curious about CPU design.

Anyone are taking the FPGA Embedded Design series by Closure Labs.

Target Audiences

Embedded designers who want to dive deeper into Soft-Processor design.

Intermediate FPGA enthusiasts who are curious about CPU design.

Anyone are taking the FPGA Embedded Design series by Closure Labs.

It’s time to take on a Challenge! How does designing a CPU sound?

In this fourth part of the FPGA Embedded Design series, we’ll design a CPU from scratch to finally get it up and running on several platforms.

We’ll write most of the code in the Vivado Design Suite, but you’ll have the chance to see it working as well in Quartus Prime, EDA Playground or LabsLand, so you can follow along with your favorite tools. The FPGA boards we’ll use are the BASYS3, by Digilent (with a Xilinx FPGA), and the DE0-CV from Terasic (with an Intel FPGA).

This course consists of three main parts:

1. Foundations of Computer Architecture, where we’ll cover the essentials of CPU design and jargon.

2. Design of our own CPU, where we’ll make several design decisions to come up with a soft processor that meets our needs.

3. Hands-On Development, where we’ll write the code, simulate and finally get our CPU into an FPGA board. No purchases are required for this part, but it sure helps to have your own board to follow along, and keep on tinkering in the future with your new soft processor.

What are you waiting for? Let’s have fun designing a CPU!!! 

Course Curriculum

Chapter 1: Introduction

Lecture 1: Introduction

Lecture 2: Instructor Introduction

Lecture 3: Motivation 1

Lecture 4: Motivation 2

Lecture 5: Motivation 3

Chapter 2: A Crash Course on Computer Architecture

Lecture 1: Parts of a Microprocessor-Based System

Lecture 2: Why we need a Bus Architecture

Lecture 3: The Bus Architecture

Lecture 4: The Data Bus

Lecture 5: The Address Bus

Lecture 6: The Control Bus

Lecture 7: How is it possible to drive a bus?

Lecture 8: The Memory Subsystem

Lecture 9: The Input/Output Subsystem

Chapter 3: Inside the CPU

Lecture 1: Parts of a CPU

Lecture 2: Arithmetic Logic Unit

Lecture 3: Registers

Lecture 4: Special Registers

Lecture 5: The Data Path

Lecture 6: Control Logic

Lecture 7: Instruction Encoding

Lecture 8: Instruction Execution

Chapter 4: Some Design Approaches

Lecture 1: CPU Design Criteria

Lecture 2: Structural vs. Behavioral Approaches

Lecture 3: Instruction Set Architecture

Lecture 4: Addressing Modes

Lecture 5: Some Addressing Mode Examples

Lecture 6: Number of Operands per Instruction

Lecture 7: CISC vs RISC Architectures

Lecture 8: Harvard vs. Von Neumann

Chapter 5: Lets Design a CPU!

Lecture 1: A Quick and Dirty Approach

Lecture 2: Program 1: Add Two Numbers

Lecture 3: Program 2: Fibonacci Sequence

Lecture 4: Program 3: Calculate a Factorial

Lecture 5: The Instructions we Need

Lecture 6: Your Personal Preferences

Lecture 7: Really, make your own choices!

Lecture 8: How many operands per instruction?

Lecture 9: CISC or RISC?

Lecture 10: Harvard or Von Neumann?

Lecture 11: System Design

Lecture 12: CPU Registers

Lecture 13: Memory Model

Lecture 14: Input/Output Model

Chapter 6: Instruction Set Design

Lecture 1: Instruction Set Design

Lecture 2: Instruction Encoding Spreadsheet

Lecture 3: Instruction Set Encoding

Lecture 4: Assembly Code for Program Example #1 (Adding Two Numbers)

Lecture 5: Assembly Code for Program Example #2 (Fibonacci Number)

Lecture 6: Assembly Code for Program Example #3 (Factorial)

Lecture 7: A Review of Addressing Modes

Lecture 8: A Review of Used Instructions

Lecture 9: Room for Growth

Chapter 7: Writing Our Own CPU RTL Code

Lecture 1: Writing your CPU RTL Code

Lecture 2: A bit of RTL and lots of Behavioral Code

Lecture 3: Registers

Lecture 4: State Machine Design

Lecture 5: Vivado Code

Lecture 6: The states of Jimmy

Lecture 7: The Opcodes

Lecture 8: Extracting the Opcode from the Instruction

Lecture 9: The Fetch Cycle

Chapter 8: Instruction Set Implementation

Lecture 1: Instruction Set Implementation

Lecture 2: Implementing the Instructions

Lecture 3: Addition

Lecture 4: Multiplication

Lecture 5: Update on MUL

Lecture 6: Register Transfer

Lecture 7: No Operation

Lecture 8: Load Immediate

Lecture 9: Compare Immediate

Lecture 10: Decrement

Lecture 11: Port Input

Lecture 12: Port Output

Lecture 13: Unconditional Branching

Lecture 14: Branch if Higher

Lecture 15: Branch on Equal

Chapter 9: System Design

Lecture 1: System Design

Lecture 2: Finishing up the System

Lecture 3: Coding in our own Machine Language

Lecture 4: Writing the Program Memory RTL

Lecture 5: Writing the Example Program #1 in our Memory

Lecture 6: Writing the Example Program #2 in our Memory

Lecture 7: Writing the Example Program #3 in our Memory

Chapter 10: Synthesis and Simulation

Lecture 1: A word on Synthesis

Lecture 2: Simulated Hardware for Program #1

Lecture 3: Simulated Hardware for Programs #2 and #3

Lecture 4: Vivado Simulation for Program #1

Lecture 5: Vivado Simulation for Program #2

Lecture 6: Vivado Simulation for Program #3

Instructors

Eduardo Corpe?o
Electrical & Computer Engineer

Marissa Siliezar
Telecom Engineer

Rating Distribution

1 stars: 2 votes

2 stars: 2 votes

3 stars: 10 votes

4 stars: 36 votes

5 stars: 58 votes

Frequently Asked Questions

How long do I have access to the course materials?

You can view and review the lecture materials indefinitely, like an on-demand channel.

Can I take my courses with me wherever I go?

Definitely! If you have an internet connection, courses on Udemy are available on any device at any time. If you don’t have an internet connection, some instructors also let their students download course lectures. That’s up to the instructor though, so make sure you get on their good side!