SOC Verification using SystemVerilog

SOC Verification using SystemVerilog, available at Free, has an average rating of 4.31, with 35 lectures, 8 quizzes, based on 6123 reviews, and has 53948 subscribers.

You will learn about Learn the important concepts in SOC/ASIC/VLSI design verification flow Learn the System Verilog language for Functional Verification usage Be ready and qualified for a Verification job in semiconductor industry Udemy Certification on successful course completion Be able to code, simulate and verify SystemVerilog Testbenches This course is ideal for individuals who are Students of VLSI, Digital and Embedded System Design, Microelectronics who wants to be ready for a job in semiconductor industry or Digital Design and Verification Professionals who are passionate about continuous learning It is particularly useful for Students of VLSI, Digital and Embedded System Design, Microelectronics who wants to be ready for a job in semiconductor industry or Digital Design and Verification Professionals who are passionate about continuous learning.

Enroll now: SOC Verification using SystemVerilog

Summary

Title: SOC Verification using SystemVerilog

Price: Free

Average Rating: 4.31

Number of Lectures: 35

Number of Quizzes: 8

Number of Published Lectures: 35

Number of Published Quizzes: 7

Number of Curriculum Items: 43

Number of Published Curriculum Objects: 42

Original Price: Free

Quality Status: approved

Status: Live

What You Will Learn

Learn the important concepts in SOC/ASIC/VLSI design verification flow

Learn the System Verilog language for Functional Verification usage

Be ready and qualified for a Verification job in semiconductor industry

Udemy Certification on successful course completion

Be able to code, simulate and verify SystemVerilog Testbenches

Who Should Attend

Students of VLSI, Digital and Embedded System Design, Microelectronics who wants to be ready for a job in semiconductor industry

Digital Design and Verification Professionals who are passionate about continuous learning

Target Audiences

Students of VLSI, Digital and Embedded System Design, Microelectronics who wants to be ready for a job in semiconductor industry

Digital Design and Verification Professionals who are passionate about continuous learning

This course introduces the concepts of System on Chip Design Verification with emphasis on Functional Verification flows and methodologies. The course also teaches how to code in SystemVerilog language – which is the most popular Hardware Description Language used for SOC design and verification in semiconductor industry. The course is organised into multiple sections and each uses short video lectures to explain the concepts. After every few other lectures -lab exercises are provided and students will be guided to practically code, simulate and verify using a free browser based Simulator and Waveform viewer. Quizzes are also added to test the students knowledge and progress.

Part 2 of the course covering advanced and industry standard verification methodologies like OVM//UVM will follow based on feedback on this course

Course Curriculum

Chapter 1: Welcome to Course – Introduction

Lecture 1: Introduction and Overview

Lecture 2: Introduction to SOC and VLSI design flows

Lecture 3: Course Resources

Chapter 2: Verification Concepts Explained

Lecture 1: Verification – What, Why and How ?

Lecture 2: Verification – Planning, Approaches, Metrics

Lecture 3: Verification Methodologies – Simulation, Formal, Assertions

Lecture 4: Directed vs Constrained Random Verification – Coverage

Lecture 5: Other Trends – HW+SW Verification, Emulation

Chapter 3: Introduction to System Verilog Language

Lecture 1: History and Language usage overview

Lecture 2: Language Constructs – Data types and Operators

Lecture 3: Language Constructs – Loops and Control Flows

Lecture 4: Tasks and Functions

Lecture 5: Arrays and Queues

Chapter 4: Basic SV TB – Connecting to your design

Lecture 1: Interfaces

Lecture 2: Clocking Blocks

Lecture 3: Program Blocks

Lecture 4: Direct Programming Interface (DPI)

Chapter 5: SV – OOP concepts and Randomization

Lecture 1: Basic OOP Concepts

Lecture 2: System Verilog Classes Explained

Lecture 3: Virtual Interfaces

Lecture 4: Random Constraints and usages – Part 1

Lecture 5: Random Constraints – Part 2

Chapter 6: Threads and Inter Process Communication

Lecture 1: Processes and Threads in System Verilog

Lecture 2: System Verilog Mailboxes

Lecture 3: Synchronization – Events and Semaphores

Chapter 7: Project Assignment – Building a Testbench for Ethernet Switch

Lecture 1: Exercise 1: Case Study on a Design to be verified

Lecture 2: Exercise 2: Coding exercise to build a Design to be Verified OR Review example

Lecture 3: Exercise 3: Coding Interfaces and Clocking Blocks to connect

Lecture 4: Exercise 4: Building Class based Testbench components

Lecture 5: Exercise 5: Connecting all TB components using mailboxes

Lecture 6: Exercise 6: Build the top TB with DUT, compile and simulate

Chapter 8: Introduction to Verification Methodologies

Lecture 1: Standard Verification Methodologies – Need and evolution

Lecture 2: Introduction to concept of OVM and UVM

Chapter 9: Course Wrapup and Summary

Lecture 1: Summary and learnings and future topics

Lecture 2: Course Improvement Survey

Instructors

Ramdas Mozhikunnath M
Expert Verification Engr, Intel Alumni, 18+ yrs exp, Author

Rating Distribution

1 stars: 84 votes

2 stars: 180 votes

3 stars: 965 votes

4 stars: 2406 votes

5 stars: 2488 votes

Frequently Asked Questions

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