Verilog HDL Through Examples

Verilog HDL Through Examples, available at $54.99, has an average rating of 4.5, with 41 lectures, based on 124 reviews, and has 7192 subscribers.

You will learn about Verilog HDL Digital Design in Verilog HDL Modelling Digital Circuits using Verilog HDL Fundamentals of Digital Electronics This course is ideal for individuals who are Digital Electronics Aspirants It is particularly useful for Digital Electronics Aspirants.

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Summary

Title: Verilog HDL Through Examples

Price: $54.99

Average Rating: 4.5

Number of Lectures: 41

Number of Published Lectures: 41

Number of Curriculum Items: 41

Number of Published Curriculum Objects: 41

Original Price: ?1,199

Quality Status: approved

Status: Live

What You Will Learn

Verilog HDL

Digital Design in Verilog HDL

Modelling Digital Circuits using Verilog HDL

Fundamentals of Digital Electronics

Who Should Attend

Digital Electronics Aspirants

Target Audiences

Digital Electronics Aspirants

Hey there, I welcome you all to my course ‘Verilog HDL through Examples’

Why Verilog?

1. To describe any digital system – microprocessor, memory, flip flop, Verilog is used. Hence it’s called as a hardware description language.

2. Using Verilog, we can model any electronic component and generate the schematic for the same.

3. For timing analysis and test analysis of circuits, Verilog is apt.

Highlights of the course:

1. Key differences between a programming language like C, C++ or Python and a hardware description language like Verilog, VHDL, SystemVerilog are clearly

2. All the fundamental concepts of Verilog are explained through standard combinational and sequential circuits.

3. Learning through examples make them very simpler to learn.

4. Proper theoretical explanation is provided for each of the circuit that is implemented in verilog in this course.

5. Testbench for each design and knowing how to test and validate them.

6. Creating Finite State Machines in Verilog.

7. Download the code and design for each of the circuits in the resources section.

8. Getting to know how to use EDA Playground for Verilog coding and how to generate the output waveform using EPWave.

9. Some of the key concepts of Verilog like

Levels of Abstraction, Two types of assignments, Producing delay, generating clock, Procedural assignments are all explained clearly.

Course Curriculum

Chapter 1: Introduction

Lecture 1: Introduction

Lecture 2: Difference between HDL and Programming Languages

Chapter 2: Understanding all the basic components of Verilog code

Lecture 1: Understanding Levels of Abstraction in Digital Design

Lecture 2: Three types of Modelling

Lecture 3: The execution flow of a Verilog code

Chapter 3: Writing our first code in Verilog – Example 1

Lecture 1: Understanding Gate Level Modelling through a simple OR Gate

Lecture 2: Difference between register and wire

Lecture 3: Writing our first testbench

Lecture 4: Interpreting our first output waveform

Chapter 4: Dataflow Modelling and Behavioral Modelling for Example 1

Lecture 1: Understanding Dataflow Modelling

Lecture 2: Understanding the behaviour of a system to code it in Behavioral Modelling

Chapter 5: Example 2 – Half adder design using all the three types of modelling

Lecture 1: Implementing Half adders using Gatelevel Modelling

Lecture 2: Implementing Half adders using Dataflow Modelling

Lecture 3: Implementing the behaviour of Half adders

Chapter 6: Example 3 – Full adder design using all the three types of modelling

Lecture 1: Full Adders using Gate Level Modelling, Working of for loop

Lecture 2: Example 3 using Dataflow Modelling

Chapter 7: Example 4 – 4 bit Parallel Adder design in Verilog

Lecture 1: 4 bit Parallel Adder Design – Theory

Lecture 2: Implementing a 4 bit Parallel Adder Circuit

Chapter 8: Example 5 – Carry Look Ahead Adder in Verilog

Lecture 1: An intuition on Propagation Delay

Lecture 2: Design Steps for Carry look ahead adder

Lecture 3: Verilog code for 4 bit Carry Look Ahead Adder

Chapter 9: Example 6 – Code Converters in Verilog

Lecture 1: Designing a BCD to Gray Code Converter {Full Design}

Lecture 2: BCD to Gray Conversion in Verilog

Chapter 10: Example 7 – Multiplexers and Demultiplexers in Verilog

Lecture 1: 37. All about Multiplexers

Lecture 2: Multiplexers and Demultiplexers in Verilog

Lecture 3: Difference between Blocking and Non Blocking type of assignments

Chapter 11: Example 8 – Flip Flop Design in Verilog

Lecture 1: Understanding the behavior of SR Flip Flops

Lecture 2: Designing a SR Flip Flop in Verilog

Lecture 3: Clock Generation in Verilog, Writing testbench for S R Flipflop

Lecture 4: Analysing the output waveform of SR Flip Flop

Lecture 5: D Flipflop in Verilog

Lecture 6: Writing a testbench for D Flip Flop

Chapter 12: Example 9 – Ones complement arithmetic (Vectors in Verilog)

Lecture 1: Introduction to Vectors (Arrays) in Verilog

Lecture 2: Detailed Implementation of Ones complement arithmetic in Verilog

Chapter 13: Example 10 – Creating a FSM in Verilog

Lecture 1: Creating a Finite State Machine in Verilog – 30 mins

Lecture 2: Testbench for the FSM

Chapter 14: Update – Sequential Circuit Modelling in Verilog

Lecture 1: Complete State Definition for a Sequence detector

Lecture 2: Verilog Code for State Diagrams

Lecture 3: State Diagram of a Traffic Light Controller

Lecture 4: Verilog code for Traffic Light Controller

Chapter 15: Resources

Lecture 1: Download the codes here!

Instructors

Sujithkumar MA
Engineer | Course Instructor

Rating Distribution

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2 stars: 3 votes

3 stars: 15 votes

4 stars: 45 votes

5 stars: 61 votes

Frequently Asked Questions

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