Building Custom AXI Interface Peripherals for ZYNQ Devices

Building Custom AXI Interface Peripherals for ZYNQ Devices, available at $49.99, has an average rating of 4, with 70 lectures, based on 62 reviews, and has 577 subscribers.

You will learn about Building custom AXI Slave Lite Interface Handling Interrupts with Custom AXI Slave Lite Interface Creating Custom AXI Stream Interface with Vivado Template Building Custom AXI Stream Interface with Verilog RTL Writing Drivers for Custom AXI Interface Interfacing of Custom AXI Interface with Zynq devices This course is ideal for individuals who are Anyone wish to build expertise in designing Custom AXI interface for Zynq Devices or Developing Hardware Accelerators with Verilog RTL It is particularly useful for Anyone wish to build expertise in designing Custom AXI interface for Zynq Devices or Developing Hardware Accelerators with Verilog RTL.

Enroll now: Building Custom AXI Interface Peripherals for ZYNQ Devices

Summary

Title: Building Custom AXI Interface Peripherals for ZYNQ Devices

Price: $49.99

Average Rating: 4

Number of Lectures: 70

Number of Published Lectures: 69

Number of Curriculum Items: 70

Number of Published Curriculum Objects: 69

Original Price: $19.99

Quality Status: approved

Status: Live

What You Will Learn

Building custom AXI Slave Lite Interface

Handling Interrupts with Custom AXI Slave Lite Interface

Creating Custom AXI Stream Interface with Vivado Template

Building Custom AXI Stream Interface with Verilog RTL

Writing Drivers for Custom AXI Interface

Interfacing of Custom AXI Interface with Zynq devices

Who Should Attend

Anyone wish to build expertise in designing Custom AXI interface for Zynq Devices

Developing Hardware Accelerators with Verilog RTL

Target Audiences

Anyone wish to build expertise in designing Custom AXI interface for Zynq Devices

Developing Hardware Accelerators with Verilog RTL

As system complexities are growing day by day, the Zynq device alone is incapable of providing the same performance and the Pure RTL module or Programmable logic (PL) needs to be integrated along with the Zynq. As Zynq works with Advanced Extensible Peripheral (AXI), it becomes mandatory for FPGA engineers to gain a fundamental understanding of adding AXI Interface to the Verilog RTL. The AXI4 offers different variants to fit diverse application needs. Understanding of the simpler variants such as AXI Lite and AXI Stream Interface lays a foundation for building an understanding of the complex AXI4 variant such as AXI Full.   

This course focuses on the usage of the Vivado IP Integrator and Vivado RTL integration for building the custom AXI interface for pure Verilog modules. There are four ways to achieve the addition of the AXI interface to the Verilog RTL viz. Using Vivado IP Packager, Vivado RTL Integration, Using System Generator, Using Vivado HLS. The course discusses two methodologies viz. Vivado IP Packager and Vivado RTL Integration in details with a simple example along with the demonstration of the integration of the created IP with the Zynq device. It will also discuss the creation of some basic device drivers, showing how software can be written to access the registers on the custom peripheral.

Course Curriculum

Chapter 1: Section 0 : Course Framework

Lecture 1: Interface Type

Lecture 2: Course Framework

Chapter 2: Building AXI Slave Lite Interface : Using Vivado Template without I/O ports

Lecture 1: Agenda

Lecture 2: Slave Lite Interface without I/O Ports P1 : Creating IP

Lecture 3: Slave Lite Interface without I/O Ports P2 : Creating IP

Lecture 4: Slave Lite Interface without I/O Ports P3 : Creating IP

Lecture 5: Slave Lite Interface without I/O Ports P4 : Creating C Application

Lecture 6: Slave Lite Interface without I/O Ports P5 : Creating C Application

Lecture 7: C Code

Chapter 3: Building AXI Slave Lite Interface : Using Vivado Template with I/O ports

Lecture 1: Agenda

Lecture 2: Adding Output port to Slave Lite Interface P1

Lecture 3: Adding Output port to Slave Lite Interface P2

Lecture 4: Adding Output port to Slave Lite Interface P3

Lecture 5: Adding Input and Output ports to Slave Lite Interface P1

Lecture 6: Adding Input and Output ports to Slave Lite Interface P2

Lecture 7: Adding Input and Output ports to Slave Lite Interface P3

Chapter 4: Understanding AXI4-Lite Signals

Lecture 1: Agenda

Lecture 2: Understanding Mandatory Signal: Master Write to Slave (Writing Ops) P1

Lecture 3: Understanding Mandatory Signal: Master Write to Slave (Writing Ops) P2

Lecture 4: Understanding Mandatory Signal: Master read from Slave (Reading Ops)

Lecture 5: Other Signals in Slave Lite Interface

Lecture 6: Block Design used in Demonstration

Lecture 7: Analyzing Signals on ILA Probe

Chapter 5: Adding AXI Lite Interface for existing Verilog Code

Lecture 1: Agenda

Lecture 2: Add Existing RTL : Delay Generator P1

Lecture 3: Add Existing RTL : Delay Generator P2

Lecture 4: Adding Existing RTL : Multiplier P1

Lecture 5: Adding Existing RTL : Multiplier P2

Lecture 6: Adding Exisitng RTL : COMPLEX FSM P1

Chapter 6: Adding Interrupts to Slave Lite Interfaces

Lecture 1: Agenda

Lecture 2: Fundamentals of Interrupt C Application

Lecture 3: Adding Interrupt with RTL P1

Lecture 4: Adding Interrupt with RTL P2

Lecture 5: Code

Chapter 7: Adding Interrupts with Vivado Template

Lecture 1: Agenda

Lecture 2: Using Vivado Interrupt Template Code P1

Lecture 3: Using Vivado Interrupt Template Code P2

Lecture 4: Code

Lecture 5: Modifying Delay of the Vivado Interrupt Template

Lecture 6: Generating Continuous Interrupt P1

Lecture 7: Generating Continuous Interrupt P2

Lecture 8: Blinking Effect with Interrupt

Lecture 9: Code

Chapter 8: Adding Master Interface

Lecture 1: Agenda

Lecture 2: Creating Master Interface with Vivado Template P1

Lecture 3: Creating Master Interface with Vivado Template P2

Lecture 4: Code

Chapter 9: AXI Stream Slave Interface with Vivado Template

Lecture 1: Agenda

Lecture 2: Building AXIS Slave Interface P1

Lecture 3: Building AXIS Slave Interface P2

Lecture 4: Code

Lecture 5: Building Complex FSM with existing FSM for AXIS

Lecture 6: Code

Chapter 10: AXI Stream Master Interface with Vivado Template

Lecture 1: Agenda

Lecture 2: Creating AXIS Master Interface P1

Lecture 3: Creating AXIS Master Interface P2

Lecture 4: Code

Chapter 11: AXIS Slave Interface with Verilog

Lecture 1: Agenda

Lecture 2: Building AXIS Slave Interface with Verilog P1

Lecture 3: Building AXIS Slave Interface with Verilog P2

Lecture 4: Building AXIS Slave Interface with Verilog P3

Lecture 5: Code and BD

Chapter 12: AXIS Master Slave Interface with Verilog

Lecture 1: Agenda

Lecture 2: Building AXIS Master Slave Interface with Verilog P1

Lecture 3: Building AXIS Master Slave Interface with Verilog P2

Lecture 4: Code and BD

Lecture 5: Code and BD

Chapter 13: Understanding Common Errors

Lecture 1: Common Error 1

Lecture 2: Common Error 2

Instructors

Kumar Khandagle
Trainer @ NAMASTE FPGA

Rating Distribution

1 stars: 1 votes

2 stars: 4 votes

3 stars: 7 votes

4 stars: 27 votes

5 stars: 23 votes

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