UVM for Verification Part 3-Register Abstraction Layer (RAL)

UVM for Verification Part 3:Register Abstraction Layer (RAL), available at $79.99, has an average rating of 4.49, with 141 lectures, based on 211 reviews, and has 2118 subscribers.

You will learn about Using UVM RAL for verification of DUT Registers and Memories Understanding different Register as well memories methods Implementing Frontdoor and Backdoor access methods Implementing Implicit and Explicit Predictor Coverage Computation for Register and Memories This course is ideal for individuals who are Engineers involved/interested in the verification of RTLs It is particularly useful for Engineers involved/interested in the verification of RTLs.

Enroll now: UVM for Verification Part 3:Register Abstraction Layer (RAL)

Summary

Title: UVM for Verification Part 3:Register Abstraction Layer (RAL)

Price: $79.99

Average Rating: 4.49

Number of Lectures: 141

Number of Published Lectures: 141

Number of Curriculum Items: 149

Number of Published Curriculum Objects: 149

Original Price: ?1,799

Quality Status: approved

Status: Live

What You Will Learn

Using UVM RAL for verification of DUT Registers and Memories

Understanding different Register as well memories methods

Implementing Frontdoor and Backdoor access methods

Implementing Implicit and Explicit Predictor

Coverage Computation for Register and Memories

Who Should Attend

Engineers involved/interested in the verification of RTLs

Target Audiences

Engineers involved/interested in the verification of RTLs

Writing Verilog test benches is always fun after completing RTL design. You can assure clients that the design will be bug-free in tested scenarios. As system complexity grows day by day, System Verilog becomes a choice for verification due to its powerful capabilities and reusability, which help verification engineers quickly locate hidden bugs. System Verilog lags behind the structured approach, whereas UVM works hard to form a general skeleton. The addition of the configuration database shifts the way we used to work with the verification language in the past. Within a few years, verification engineers recognized the capabilities of UVM and adopted it as a de facto standard for RTL design verification. The UVM will have a long run in the verification domain; hence, learning about the UVM will help VLSI aspirants pursue a career in this domain.

The UVM Register layer provides a set of libraries for adopting UVM for verification of DUTs consisting of registers as well as memories. UVM RAL provides a set of abstract methods to access the register as well as memories with either a front-door or back-door access mechanism that are easy to use as well as configurable. We will also be covering the coverage computation we get with UVM RAL.

 

Course Curriculum

Chapter 1: Adding Register and Memory to Verification Environment

Lecture 1: Course Overview

Lecture 2: Agenda

Lecture 3: Advantage of UVM RAL P1

Lecture 4: Advantage of UVM RAL P2

Lecture 5: Advantage of UVM RAL P3

Lecture 6: Advantage of UVM RAL P4

Lecture 7: When to use RAL in Verification environment

Lecture 8: Code

Lecture 9: Components of Register model P1

Lecture 10: Components of Register model P2

Lecture 11: Components of Register model P3

Lecture 12: Notes

Lecture 13: Typical Learning Path

Lecture 14: Understanding different types of registers

Lecture 15: Implementation of Register in Verification Environmnet P1

Lecture 16: Implementation of Register in Verification Environmnet P2

Lecture 17: Alternate way of adding configure function

Lecture 18: Summary : Configure function

Lecture 19: Implementation of Register in Verification Environmnet P3

Lecture 20: Code

Lecture 21: Slides

Lecture 22: Adding Register with two fields

Lecture 23: Code

Lecture 24: Adding Register with reserved bits

Lecture 25: Code

Lecture 26: Different Access Policy P1

Lecture 27: Different Access Policy P2

Lecture 28: Different Access Policy P3

Lecture 29: Different Access Policy P4

Lecture 30: Notes

Lecture 31: Adding Memory P1

Lecture 32: Adding Memory P2

Lecture 33: Code

Lecture 34: Slides

Chapter 2: Adding Register Block

Lecture 1: Agenda

Lecture 2: Adding Register Block P1

Lecture 3: Adding Register Block P2

Lecture 4: Adding Register Block P3

Lecture 5: Code

Lecture 6: Slides

Chapter 3: Understanding Adapter

Lecture 1: Agenda

Lecture 2: Usage of adapter

Lecture 3: Typical flow

Lecture 4: Structure of uvm_reg_bus_op struct

Lecture 5: Complete flow

Lecture 6: Understanding reg2bus

Lecture 7: Understanding bus2reg

Lecture 8: Adapter code with native memory ports P1

Lecture 9: Adapter code with native memory ports P2

Lecture 10: Adapter code with Protocol Specific ports P1

Lecture 11: Adapter code with Protocol Specific ports P2

Lecture 12: Summary

Lecture 13: Slides

Chapter 4: Different Register Method

Lecture 1: Agenda

Lecture 2: Types of Predictor : Implicit Predictor

Lecture 3: Types of Predictor : Explicit Predictor

Lecture 4: Types of Predictor : Passive Predictor

Lecture 5: Slide

Lecture 6: Driver Sequencer Communication

Lecture 7: Code

Lecture 8: Understanding Design

Lecture 9: Adding Driver + Sequencer

Lecture 10: Adding Agent

Lecture 11: Adding Register Model

Lecture 12: Adding env + uvm test top + testbench top

Lecture 13: Executing Code

Lecture 14: Design Code

Lecture 15: Understanding Desired and Mirrored Values

Lecture 16: Different register methods

Lecture 17: Working with Desired Value

Lecture 18: Testbench Code

Lecture 19: Working with Mirrored Value

Lecture 20: Testbench Code

Lecture 21: Understanding predict and mirror

Lecture 22: Demonstration

Lecture 23: Testbench Code

Lecture 24: Single Read and Write Transaction

Lecture 25: Multiple Read and Write Transaction

Lecture 26: Testbench Code

Lecture 27: Using randomize

Lecture 28: Testbench Code

Lecture 29: Understanding Reset Methods

Lecture 30: Demonstration

Lecture 31: Testbench Code

Lecture 32: Connecting reset methods to DUT

Lecture 33: Testbench Code

Chapter 5: Different ways of accessing Register and Memories

Lecture 1: Agenda

Lecture 2: Type of access methods p1: Frontdoor

Lecture 3: Type of access methods p2: Backdoor

Lecture 4: Frontdoor Demonstration

Instructors

Kumar Khandagle
Trainer @ NAMASTE FPGA

Rating Distribution

1 stars: 2 votes

2 stars: 1 votes

3 stars: 17 votes

4 stars: 67 votes

5 stars: 124 votes

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