Learn VHDL Design using Xilinx Zynq-7000 ARMFPGA SoC

Learn VHDL Design using Xilinx Zynq-7000 ARM/FPGA SoC, available at $49.99, has an average rating of 3.85, with 34 lectures, 8 quizzes, based on 207 reviews, and has 5859 subscribers.

You will learn about Describe and explain VHDL syntax and semantics Create synthesizable designs using VHDL Use Xilinx FPGA development board for hand-on experience Design simple and practical test benches in VHDL Use the Xilinx Vivado toolset Design and develop VHDL models This course is ideal for individuals who are Engineers or Hobbyists or Makers or Engineering Students or Engineering Managers It is particularly useful for Engineers or Hobbyists or Makers or Engineering Students or Engineering Managers.

Enroll now: Learn VHDL Design using Xilinx Zynq-7000 ARM/FPGA SoC

Summary

Title: Learn VHDL Design using Xilinx Zynq-7000 ARM/FPGA SoC

Price: $49.99

Average Rating: 3.85

Number of Lectures: 34

Number of Quizzes: 8

Number of Published Lectures: 34

Number of Published Quizzes: 8

Number of Curriculum Items: 42

Number of Published Curriculum Objects: 42

Original Price: $29.99

Quality Status: approved

Status: Live

What You Will Learn

Describe and explain VHDL syntax and semantics

Create synthesizable designs using VHDL

Use Xilinx FPGA development board for hand-on experience

Design simple and practical test benches in VHDL

Use the Xilinx Vivado toolset

Design and develop VHDL models

Who Should Attend

Engineers

Hobbyists

Makers

Engineering Students

Engineering Managers

Target Audiences

Engineers

Hobbyists

Makers

Engineering Students

Engineering Managers

  Teach yourself the analysis and synthesis of digital systems using VHDL to design and simulate FPGA, ASIC, and VLSI digital systems. Participants learn the fundamental concepts of VHDL and practical design techniques using a Xilinx FPGA Development Board and simulation software for hands-on experience. The VHDL methodology and design flow for logic synthesis addresses design issues related to component modeling, data flow description in VHDL and behavioral description of hardware. An emphasis is placed on understanding the hardware description language, VHDL design techniques for logic synthesis, design criteria, and VHDL applications. 

  At the end of this course, participants will be able to accomplish the following: 

Describe and explain VHDL syntax and semantics

Create synthesizable designs using VHDL

Use Digilent Zybo Z7: Zynq-7000 ARM/FPGA SoC Development Board for hand-on experience

Use the Xilinx Vivado toolset

Design simple and practical test-benches in VHDL

Design and develop VHDL models

  Prerequisites: 

Familiarity with digital logic design, electrical engineering, or equivalent experience.

  Even if you’re now already familiar with VHDL but you’ve: 

Never used an attribute other than ‘event?

Never used variables?

Always used a process where a single concurrent statement would have sufficed?

Never used assert or report statements except (maybe) in a test-bench?

Never used an unconstrained vector or array?

Never used a passive process inside of an entity?

Never used a real or the math_real library package in synthesizable code?

Always used a single process per signal assignment?

  then this course will definitely have something for you as well.  You will learn finite state machine design, the two-process design methodology, test-bench design, combinatorial and sequential logic, and extensible synthesizable designs that are reusable. 

Course Curriculum

Chapter 1: Basics

Lecture 1: Intro

Lecture 2: Design Units

Lecture 3: Comments

Lecture 4: Identifiers

Lecture 5: Literals

Lecture 6: Xilinx Software Tool Installation

Chapter 2: Data types & operations

Lecture 1: Data Object Classes

Lecture 2: Scalar Data Types

Lecture 3: Operators

Lecture 4: Composite Data Types

Lecture 5: Xilinx Zybo Z7 Xor Demo

Chapter 3: Concurrent statements

Lecture 1: Design Units

Lecture 2: Concurrent Statements

Lecture 3: Demo 2

Chapter 4: Sequential statements

Lecture 1: Sequential Statements

Lecture 2: Wait Statements

Lecture 3: Conditional Statements

Lecture 4: Loop Statements

Lecture 5: Assert & Report Statements

Chapter 5: Processes

Lecture 1: Test Benches

Lecture 2: Processes

Lecture 3: State Machines

Lecture 4: BasicFSM Demo

Chapter 6: Subprograms

Lecture 1: Functions

Lecture 2: Procedures

Chapter 7: Packages

Lecture 1: Packages, Components, and Configuration

Lecture 2: ColorFSM Demo

Chapter 8: Design for synthesis

Lecture 1: Design for Synthesis & Demo

Chapter 9: Advanced topics

Lecture 1: Life Demo

Lecture 2: Aliases

Lecture 3: Generics

Lecture 4: Generate Statements

Chapter 10: Additional libraries

Lecture 1: NewLife Demo

Lecture 2: Additional Libraries

Instructors

Clyde R. Visser, P.E.
Embedded Systems, ASIC, and FPGA Engineer

Rating Distribution

1 stars: 11 votes

2 stars: 23 votes

3 stars: 48 votes

4 stars: 63 votes

5 stars: 62 votes

Frequently Asked Questions

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