Effective Verilog Learning with Intel FPGAs

Effective Verilog Learning with Intel FPGAs, available at $84.99, has an average rating of 4.55, with 86 lectures, 8 quizzes, based on 73 reviews, and has 435 subscribers.

You will learn about Hardware Description Language ( in this case, Verilog), different design constructs, efficient development handling, TCL for Verification-Automation etc Our basic target will be Intel FPGAs and Development tools. A small part regarding Xilinx FPGAs is also included. The goal of this course is to train young professionals for independent development. All Examples and software will be done in Windows (10) environment. Students with Windows 7 and 8 may also join the course. (Sorry Linux Guys) Development board is optional. All Software used in this course is freely available. But a computer with Windows Operating system is a must. We will analyze already developed codes, so that I may have time to explain codes and syntax in more detail. This step I took to shrink course duration. 2 Intel FPGA based development Boards are introduced. 1 Xilinx FPGA based development Board and Xilinx tool chain is also introduced. This course is ideal for individuals who are Beginners and Hobbyists. In fact, any one who is curious. But keep in mind, this is a technical course. or This course gives a practical go through with the FPGA development phases. So, if you have some urgent assignment, and you dont have much background in FPGA development, then may be this course can help you in solving that. or Professionals, who already know Microcontrollers, and want to try FPGAs as well. or I kept this course as cheap as possible, so that most student can benefit from it. or Not suitable for Professional FPGA developers !!! It is particularly useful for Beginners and Hobbyists. In fact, any one who is curious. But keep in mind, this is a technical course. or This course gives a practical go through with the FPGA development phases. So, if you have some urgent assignment, and you dont have much background in FPGA development, then may be this course can help you in solving that. or Professionals, who already know Microcontrollers, and want to try FPGAs as well. or I kept this course as cheap as possible, so that most student can benefit from it. or Not suitable for Professional FPGA developers !!!.

Enroll now: Effective Verilog Learning with Intel FPGAs

Summary

Title: Effective Verilog Learning with Intel FPGAs

Price: $84.99

Average Rating: 4.55

Number of Lectures: 86

Number of Quizzes: 8

Number of Published Lectures: 86

Number of Published Quizzes: 8

Number of Curriculum Items: 94

Number of Published Curriculum Objects: 94

Original Price: 19.99

Quality Status: approved

Status: Live

What You Will Learn

Hardware Description Language ( in this case, Verilog), different design constructs, efficient development handling, TCL for Verification-Automation etc

Our basic target will be Intel FPGAs and Development tools. A small part regarding Xilinx FPGAs is also included.

The goal of this course is to train young professionals for independent development.

All Examples and software will be done in Windows (10) environment. Students with Windows 7 and 8 may also join the course. (Sorry Linux Guys)

Development board is optional. All Software used in this course is freely available. But a computer with Windows Operating system is a must.

We will analyze already developed codes, so that I may have time to explain codes and syntax in more detail. This step I took to shrink course duration.

2 Intel FPGA based development Boards are introduced. 1 Xilinx FPGA based development Board and Xilinx tool chain is also introduced.

Who Should Attend

Beginners and Hobbyists. In fact, any one who is curious. But keep in mind, this is a technical course.

This course gives a practical go through with the FPGA development phases. So, if you have some urgent assignment, and you dont have much background in FPGA development, then may be this course can help you in solving that.

Professionals, who already know Microcontrollers, and want to try FPGAs as well.

I kept this course as cheap as possible, so that most student can benefit from it.

Not suitable for Professional FPGA developers !!!

Target Audiences

Beginners and Hobbyists. In fact, any one who is curious. But keep in mind, this is a technical course.

This course gives a practical go through with the FPGA development phases. So, if you have some urgent assignment, and you dont have much background in FPGA development, then may be this course can help you in solving that.

Professionals, who already know Microcontrollers, and want to try FPGAs as well.

I kept this course as cheap as possible, so that most student can benefit from it.

Not suitable for Professional FPGA developers !!!

This course is designed to make students confident developers of Digital Systems using Verilog and AMD and  Intel FPGAs (2 different boards and FPGAs). Every aspect is discussed from different angles so that the whole concept becomes clearer. This course uses two cheap Intel FPGA development boards and a Digilent(AMD) board along with freely available software(Quartus Lite, ModelSim, Vivado). Purchasing of boards is absolutely optional. This course can be done without development boards.

Additionally, FPGAs and toolchains from other vendors are also introduced briefly.

This course takes you through:

Design using Verilog HDL (in the simplest possible ways)

Tool setup, which is the hardest part.

Tool automation introduces the techniques that I learned over the years.

Different FPGA architectures

Managerial side of choosing parts for development

Simulation makes sure whether the design is correctly made

And above all, I share the experience that I gained over the years.

As a word of caution: I have not updated this course for a long time. The Toolchains of both Xilinx(now AMD) and Quartus have evolved a bit. Please try to download the tools and if you don’t understand the tool setup ask for your money asap without wasting time. I teach as a hobby, and teaching is one of my passions. Feel free to request, upgrades or any help. I am here for you.

Enjoy and rock and roll in your career.

Course Curriculum

Chapter 1: Introductions

Lecture 1: Introduction to the Course

Lecture 2: What is FPGA

Lecture 3: How to Choose a FPGA

Lecture 4: Part numbers, Pin Numbers of FPGAs

Lecture 5: Selecting a Development board

Lecture 6: Details on MAX1000 baord

Lecture 7: Details on De0-Nano board

Lecture 8: I/O pins

Lecture 9: Clock pins

Lecture 10: JTAG Interface pins

Lecture 11: Power pins, pin Banks, Drive-Powers

Chapter 2: Software Installations

Lecture 1: Installing Quartus II Prime (Lite/Free) and ModelSim

Lecture 2: Installing USB blaster software for DE0-Nano

Lecture 3: Installing USB blaster software for MAX1000

Chapter 3: Introduction to Hardware Description Language(HDL)

Lecture 1: Introduction to Hardware Description Languages (HDLs)

Lecture 2: Verilog Fundamentals 1

Lecture 3: Verilog Fundamentals 2

Lecture 4: Verilog Fundamentals 3

Lecture 5: Verilog Fundamentals 4

Lecture 6: Verilog Fundamentals 5

Lecture 7: Verilog Fundamentals 6 : Operators

Lecture 8: D Flip-flop theory

Lecture 9: Our beloved D Flip-flop : ModelSim

Lecture 10: Testbench theory

Lecture 11: Verification of D Flip-flop In ModelSim: The RTL Simulation

Lecture 12: Introduction to Quartus II Lite software

Lecture 13: Programming Max1000 board with D-Flip Flop

Lecture 14: Programming DE0-Nano with D-Flip Flop

Lecture 15: Gates

Lecture 16: Multi-gate designs

Lecture 17: Full Adder and multi-bit adder : The Instances in Verilog

Lecture 18: Post Fitting or Gate level simulation using Testbench using Quartus-ModelSim

Chapter 4: HDL Design Constructs with Examples

Lecture 1: HDL: The MUX Example

Lecture 2: Simple MAC (Multiplication And Accumulation) block

Lecture 3: MAC testing

Lecture 4: Counter Design

Lecture 5: Counter Verification

Lecture 6: Programming Counter in DE0 Nano

Lecture 7: Programming Counter in MAX1000

Lecture 8: Introduction to ATOM Editor

Lecture 9: Two always blocks : Code Style explained

Lecture 10: Encoders

Lecture 11: Parameterized Designs: RAM design

Lecture 12: RAM testing

Lecture 13: Case Constructs

Lecture 14: Case Example and verification

Lecture 15: Synthesizable, and non-Synthesizable Verilog

Chapter 5: TCL Language and Testing Automation

Lecture 1: TCL Introduction

Lecture 2: Verification automation using TCL: Method 1

Lecture 3: Verification automation using TCL: Method 2

Chapter 6: Some Quartus options

Lecture 1: Introduction to Qsys and IP Catalog

Lecture 2: Using IP Catalog

Lecture 3: FPGA Block resources and Testing of Integrated cores

Lecture 4: Quartus Primitives / Standard Verilog Primitives

Lecture 5: Introduction to SDC files

Lecture 6: Writing and Adding SDC files into Quartus a Project

Chapter 7: Advance Topics and UART Project

Lecture 1: State Machine concept

Lecture 2: Free-Running Finite State Machine (FRFSM)

Lecture 3: FRFSM : Coding

Lecture 4: FRFSM : Testbench testing

Lecture 5: FRFSM : Board testing

Lecture 6: Event Driven Finite State Machines

Lecture 7: Event Driven Finite State Machines: Testing using Board

Lecture 8: Multi Event Driven State machine

Lecture 9: Multi Event Driven State machine : Coding

Lecture 10: Dynamic Testbenche

Lecture 11: UART Theory: Tx and Rx

Lecture 12: UART Tx Coding

Lecture 13: Verification on Board and Computer

Lecture 14: UART Rx Coding

Lecture 15: Verification on Board and Computer

Lecture 16: Combining Tx and Rx

Chapter 8: Conclusion: Intel Part

Lecture 1: Way forward

Chapter 9: Additional Resources 1: Xilinx Tool chain and FPGAs

Lecture 1: Introduction

Lecture 2: Xilinx 7 series FPGAs part numbers and Architecture

Lecture 3: Xilinx Arty S7-25 board by Digilent

Lecture 4: Xilinx Vivado Installation

Lecture 5: Counter Simulation on Xilinx Vivado

Lecture 6: Counter example on Arty S7-25

Lecture 7: Power types, Power banks

Lecture 8: State Machine on Arty S7-25

Lecture 9: Using SPARTAN 7 Block RAM and Verification

Lecture 10: Verilog Tasks and SystemVerilog Assertions

Instructors

Muhammad Tahir Rana
Sensor (ASIC) developer and Verification Engineer.

Rating Distribution

1 stars: 1 votes

2 stars: 3 votes

3 stars: 11 votes

4 stars: 23 votes

5 stars: 35 votes

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