VSD Physical Design Webinar using EDA tool 'Proton'

VSD – Physical Design Webinar using EDA tool 'Proton', available at $34.99, has an average rating of 4.5, with 23 lectures, based on 97 reviews, and has 1557 subscribers.

You will learn about Build, Verify and PNR any design, for which you have an RTL Characterize any post-layout design in terms of frequency, net count, instance count, runtime and many more Do entire floorplanning of chip online using steps mentioned in webinar This course is ideal for individuals who are Anyone who wants to learn chip designing using industry grade EDA tool or Anyone who has the limitation of tool installation and wants to design chip online It is particularly useful for Anyone who wants to learn chip designing using industry grade EDA tool or Anyone who has the limitation of tool installation and wants to design chip online.

Enroll now: VSD – Physical Design Webinar using EDA tool 'Proton'

Summary

Title: VSD – Physical Design Webinar using EDA tool 'Proton'

Price: $34.99

Average Rating: 4.5

Number of Lectures: 23

Number of Published Lectures: 23

Number of Curriculum Items: 23

Number of Published Curriculum Objects: 23

Original Price: $84.99

Quality Status: approved

Status: Live

What You Will Learn

Build, Verify and PNR any design, for which you have an RTL

Characterize any post-layout design in terms of frequency, net count, instance count, runtime and many more

Do entire floorplanning of chip online using steps mentioned in webinar

Who Should Attend

Anyone who wants to learn chip designing using industry grade EDA tool

Anyone who has the limitation of tool installation and wants to design chip online

Target Audiences

Anyone who wants to learn chip designing using industry grade EDA tool

Anyone who has the limitation of tool installation and wants to design chip online

Be it in any field – Change is inevitable. Let’s change the way we used to do Physical design. This time, no need to install tools on laptop, no licenses needed, no hidden costs, just your gmail login id and you are ready to design your first chip online. Find it hard to believe??

I welcome you to my first “Physical Design” Webinar that happened on 20th Jan 2018 at 9am IST. This is 3-hour action-packed webinar with myself being the host and below 3 people from industry

Rajeev Srivastava –

Rajeev is technical advisor to webchip and also was one of the
developers of Proton while at Silverline Inc. Currently he is a Sr
Principal Physical Design Engineer at NXP.? While at Silverline, he was a
expert user of Proton and has worked with customers to use proton
successfully on many chip design projects. He will be helping with the
webinar today and show how to run the tools and also answer proton
related questions.

Aditya Pratap –

Aditya is the main developer and chief architect of Webchip.He was
also one of the main developers of open source EDA tool proton that we
will see in action today in our webinar.

Sanjeev Gupta –

Sanjeev is an VLSI & System design expert and also chief of operations at webchip.

Finally one word – ‘LIVE’ – pin placement, verification and routing
on WEB. All with zero license fee using industry grade EDA tool. That’s
innovation. This is something which has never happened before.

Learn from the best, and expect a shift in your professional thinking.

I will see you all in webinar and happy learning

Course Curriculum

Chapter 1: Introduction

Lecture 1: Introduction

Chapter 2: 'Proton' features and capabilities

Lecture 1: Introduction to webchip.in

Lecture 2: Launch EDA tool 'Proton' LIVE on web

Chapter 3: RTL Design functionality verification and view physical cells

Lecture 1: Multiplier functionality description

Lecture 2: Functionality verification using iverilog on 'Proton'

Lecture 3: Import physical cells and view LEF

Lecture 4: LIVE Q&A with participants regarding LEF

Chapter 4: RTL Synthesis steps and Q&A

Lecture 1: Synthesis using 'qflow yosys'

Lecture 2: LIVE QnA with participants regarding synthesis algorithm

Lecture 3: Pre-layout timing analysis and LIVE QnA

Chapter 5: Floorplanning and power planning strategies

Lecture 1: Floorplanning concept and demonstration

Lecture 2: Detail discussion on power and gnd rails location

Lecture 3: LIVE QnA with participants regarding power planning

Chapter 6: Placement and Routing steps using 'Proton'

Lecture 1: Cell and automated pin placement concept and demo using graywolf

Lecture 2: LIVE QnA with participants regarding cell and pin placement

Lecture 3: Analyze placement and clock tree synthesis & demo flylines

Lecture 4: More LIVE QnA on flylines and demo routing step

Lecture 5: Commands to analyze and report routing statistics

Chapter 7: Post layout STA and future work

Lecture 1: Post layout timing analysis steps and discussion on new feature enablement

Lecture 2: LIVE QnA discussion with participants regarding timing ECO

Lecture 3: Assignment details and upcoming webinars announcement

Lecture 4: Plan going further and future tentative tool enhancements

Chapter 8: Conclusion

Lecture 1: Conclusion

Instructors

Kunal Ghosh
Digital and Sign-off expert at VLSI System Design(VSD)

Rajeev Srivastava
Semiconductor and Automation Engineer

Rating Distribution

1 stars: 4 votes

2 stars: 7 votes

3 stars: 11 votes

4 stars: 41 votes

5 stars: 34 votes

Frequently Asked Questions

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