VSD Static Timing Analysis II

VSD – Static Timing Analysis – II, available at $49.99, has an average rating of 4.19, with 37 lectures, based on 721 reviews, and has 4938 subscribers.

You will learn about Students will be able to do a real full chip static timing analysis with $0 spent, as designs and tools used in this course are opensource Students will be able to appreciate power of opensource EDA tools, like Opentimer used in this course, and help in contributing towards the development Students can explore commercial tools with knowledge and concepts from this course, quite easily Manage a entire chip timing signoff This course is ideal for individuals who are Anyone who has completed static timing analysis – part 1 course or Anyone (with 100% static timing analysis – part 1 course completed) who has basic knowledge on flipflops, gates and digital logic It is particularly useful for Anyone who has completed static timing analysis – part 1 course or Anyone (with 100% static timing analysis – part 1 course completed) who has basic knowledge on flipflops, gates and digital logic.

Enroll now: VSD – Static Timing Analysis – II

Summary

Title: VSD – Static Timing Analysis – II

Price: $49.99

Average Rating: 4.19

Number of Lectures: 37

Number of Published Lectures: 37

Number of Curriculum Items: 37

Number of Published Curriculum Objects: 37

Original Price: $84.99

Quality Status: approved

Status: Live

What You Will Learn

Students will be able to do a real full chip static timing analysis with $0 spent, as designs and tools used in this course are opensource

Students will be able to appreciate power of opensource EDA tools, like Opentimer used in this course, and help in contributing towards the development

Students can explore commercial tools with knowledge and concepts from this course, quite easily

Manage a entire chip timing signoff

Who Should Attend

Anyone who has completed static timing analysis – part 1 course

Anyone (with 100% static timing analysis – part 1 course completed) who has basic knowledge on flipflops, gates and digital logic

Target Audiences

Anyone who has completed static timing analysis – part 1 course

Anyone (with 100% static timing analysis – part 1 course completed) who has basic knowledge on flipflops, gates and digital logic

In static timing analysis – part 1 course, we introduced you to basic and essential timing checks, like cppr, gba, pba, etc. In this course, we are focusing on application of these concepts on real chip using opensource sta tool called ‘Opentimer’. There is an amount of homework needed to make this tool work, but you know what, looking and feeling the power of this opensource tool, you will find the effort is worth taking

Why its worth? Because, you can now analyze your chip at $0 right from your home. Isn’t that FREEdom that we have been looking for? In my advanced courses, including this one, the prime focus is on how to analyze complex chips like USB controller or DDR using Opentimer.

Opentimer has been developed by Tsung-Wei Huang and Prof. Martin D. F. Wong in the University of Illinios at Urbana-Champaign (UIUC), IL, USA. It supports important features like PBA, CPPR, block based analysis, and many more.?

I am using this tool in this course for explaining the concepts from STA-part 1 and also for some interface analysis that we will be looking in this course.

So, hope you enjoy learning this course in the same way we enjoyed making them.

Happy Learning !!

Course Curriculum

Chapter 1: Introduction to sta-2 and opentimer tool

Lecture 1: Introduction to sta-2

Lecture 2: Introduction to opentimer, netlist definition and my_run.tcl creation

Chapter 2: Constraints creation commands for Opentimer

Lecture 1: Clock creation and clock arrival time definitions

Lecture 2: Input delay constraints for interface setup/hold analysis

Lecture 3: Clock slew and data slew constraints

Lecture 4: Output load and output delay constraints

Lecture 5: my_run.tcl for above experiments

Chapter 3: Full reg2reg analysis using OpenTimer tool

Lecture 1: Actual arrival time (AAT) and required arrival time (RAT) calculation basics

Lecture 2: my_netlist.v for above lecture

Lecture 3: my_netlist.timing for above lecture

Lecture 4: Slack compute, pesimissim (cppr) and engineering change order (eco)

Lecture 5: updated my_netlist.v for above lecture

Lecture 6: updated my_netlist.timing for above lecture

Lecture 7: blank.spef

Chapter 4: Interface analysis

Lecture 1: Introduction to interface analysis

Lecture 2: Case1 : C2Q and combinational delay for input is known

Lecture 3: Case2 : Input waveform specifications given

Lecture 4: Case 3 : setup_time, hold_time and combinational delay for output is known

Lecture 5: Hold fixing ECO and Case 4: Output waveform specifications known

Lecture 6: updated my_netlist.v and hold eco script for above interface analysis

Lecture 7: Case 5 : Source synchronous interface analysis for setup

Lecture 8: Source synchronous interface setup analysis in Opentimer tool

Lecture 9: Source synchronous interface hold analysis

Chapter 5: Clock gating analysis

Lecture 1: Introduction to clock gating analysis

Lecture 2: Active high clock gating analysis

Lecture 3: Active low clock gating analysis

Lecture 4: Latch based clock gating technique

Lecture 5: Integrated clock gating (ICG) cell

Chapter 6: Asynchronous and data checks

Lecture 1: Inception of asynchronous reset design technique

Lecture 2: How reset synchronizers resolves reset deassertion

Lecture 3: Data-to-data setup and hold check

Lecture 4: Sequential and clock tree min pulse width check

Chapter 7: Latch timing and load/slew analysis

Lecture 1: Introduction to positive and negative latch behavior

Lecture 2: Reg2Latch path with 'time borrow' and 'time given' examples

Lecture 3: Introduction to different kinds of power

Lecture 4: (Snippet for CTS course) Load and slew inter-dependence

Chapter 8: Conclusion

Lecture 1: Conclusion, acknowledgements and what next!!!

Instructors

Kunal Ghosh
Digital and Sign-off expert at VLSI System Design(VSD)

Rating Distribution

1 stars: 19 votes

2 stars: 25 votes

3 stars: 120 votes

4 stars: 260 votes

5 stars: 297 votes

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