STA and Timing Constraints

STA and Timing Constraints, available at $199.99, has an average rating of 4.3, with 26 lectures, based on 15 reviews, and has 18 subscribers.

You will learn about Understand various STA checks for timing closure Understand Basics of Timing Constraints Ability to answer STA related interview questions Understand additional checks done in STA This course is ideal for individuals who are College students, beginners and professionals working in VLSI field It is particularly useful for College students, beginners and professionals working in VLSI field.

Enroll now: STA and Timing Constraints

Summary

Title: STA and Timing Constraints

Price: $199.99

Average Rating: 4.3

Number of Lectures: 26

Number of Published Lectures: 26

Number of Curriculum Items: 26

Number of Published Curriculum Objects: 26

Original Price: $199.99

Quality Status: approved

Status: Live

What You Will Learn

Understand various STA checks for timing closure

Understand Basics of Timing Constraints

Ability to answer STA related interview questions

Understand additional checks done in STA

Who Should Attend

College students, beginners and professionals working in VLSI field

Target Audiences

College students, beginners and professionals working in VLSI field

Learn STA and Timing Constraints Concepts Deeply by vlsideepdive.

We are on a mission to inspire and develop people to achieve their goals in professional life. We enable people to learn deeply through bite-sized, interactive learning experiences. Our courses are structured and designed by leading experts in their respective fields.

Course Created by Industry Expert: Vikas Sachdeva

Vikas Sachdeva is a semiconductor design professional with more than 17 years of experience in the VLSI Industry. He was worked in the design, development, and deployment of multiple static and constraints products.

The webinar covers all basic concepts in Static Timing Analysis and Timing Constraints

Introduction to Static Timing Analysis

Timing Paths

Startpoint, Endpoint, Combinational Logic

Setup and Hold Check Definition

Understanding details of setup slack calculation

Multiple types of Timing Paths

Design Rule Checks

Timing checks on Async Pins

Clock Gating Checks

Timing Latches

STA in presence of Multiple Clocks

Timing Arcs

Cell Delays and Models

Impact of clock network on STA

Understanding Text Report in STA

Overview of SDC

Clock and Generated Clock Definitions

Clock Groups

Clock Characteristics Specification

Port Delays

Timing Exceptions

Other SDC commands

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Course Curriculum

Chapter 1: Introduction

Lecture 1: Introduction

Chapter 2: STA Definition

Lecture 1: STA Definition

Chapter 3: Timing Paths

Lecture 1: Timing Paths

Chapter 4: Elements of timing paths

Lecture 1: Elements of timing paths

Chapter 5: Setup and Hold checks

Lecture 1: Setup and Hold checks

Chapter 6: Slack calculation

Lecture 1: Slack calculation

Chapter 7: Other timing checks

Lecture 1: Other timing checks

Chapter 8: Design Rule Checks

Lecture 1: Design Rule Checks

Chapter 9: Checks on Async Pins

Lecture 1: Checks on Async Pins

Chapter 10: Clock Gating Checks

Lecture 1: Clock Gating Checks

Chapter 11: Latch timing

Lecture 1: Latch timing

Chapter 12: Multiple clocks

Lecture 1: Multiple clocks

Chapter 13: Timing arcs and Timing Sense

Lecture 1: Timing arcs and Timing Sense

Chapter 14: Cell Delays and Clock Network

Lecture 1: Cell Delays and Clock Network

Chapter 15: Setup and Hold checks detailed understanding

Lecture 1: Setup and Hold checks detailed understanding

Chapter 16: STA Text Report

Lecture 1: STA Text Report

Chapter 17: Crosstalk and Noise

Lecture 1: Crosstalk and Noise

Chapter 18: Operating Modes and other variations

Lecture 1: Operating Modes and other variations

Chapter 19: SDC Overview

Lecture 1: SDC Overview

Chapter 20: Clock definitions

Lecture 1: Clock definitions

Chapter 21: Generated Clocks

Lecture 1: Generated Clocks

Chapter 22: Clock Groups

Lecture 1: Clock Groups

Chapter 23: Clock Properties

Lecture 1: Clock Properties

Chapter 24: Boundary Constraints

Lecture 1: Boundary Constraints

Chapter 25: Timing Exceptions

Lecture 1: Timing Exceptions

Chapter 26: Mode specific constraints

Lecture 1: Mode specific constraints and other sdc commands

Instructors

Vikas Sachdeva
Trainer at vlsideepdive

Rating Distribution

1 stars: 0 votes

2 stars: 2 votes

3 stars: 1 votes

4 stars: 9 votes

5 stars: 3 votes

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