Building a Processor with Verilog HDL from Scratch

Building a Processor with Verilog HDL from Scratch, available at $54.99, has an average rating of 4.5, with 64 lectures, based on 135 reviews, and has 868 subscribers.

You will learn about Startegies to implement Verilog based CPU Buliding Custom Intruction Set to meet resource utilizations Strategies to add Program and Data Memory inside Processor Strategies to add Jump and Branching Instructions inside Processor This course is ideal for individuals who are Anyone Interested to build Custom CPU on FPGA for Load Sharing It is particularly useful for Anyone Interested to build Custom CPU on FPGA for Load Sharing.

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Summary

Title: Building a Processor with Verilog HDL from Scratch

Price: $54.99

Average Rating: 4.5

Number of Lectures: 64

Number of Published Lectures: 64

Number of Curriculum Items: 67

Number of Published Curriculum Objects: 67

Original Price: ?1,499

Quality Status: approved

Status: Live

What You Will Learn

Startegies to implement Verilog based CPU

Buliding Custom Intruction Set to meet resource utilizations

Strategies to add Program and Data Memory inside Processor

Strategies to add Jump and Branching Instructions inside Processor

Who Should Attend

Anyone Interested to build Custom CPU on FPGA for Load Sharing

Target Audiences

Anyone Interested to build Custom CPU on FPGA for Load Sharing

Most of the 21st-century applications require powerful hardware but also along with the centralized controller allowing the development of complex algorithms. As we enter into the AI or Cloud-based devices and as systems complexity is growing daily, the need for incorporating multiple processor instances becomes mandatory as we progress in the AI era. Zynq and Microblaze are two popular alternatives that exist in the market suitable for almost any application requirements. The requirements of using Multiple instances of Processor viz. Multiple instances of Microblaze soft processor or using a hard processor such as Zynq Processor along with single or multiple instances of  Microblazer become necessary to independently handle both Data processing and control requirements. The fundamental challenge of incorporating multiple instances of Soft processors like Microblaze is the number of resources consumed for implementing Microblaze on the FPGA. Since FPGA consists of a limited amount of the FPGA resources, hardware and Software partition plays a prominent role in building complex systems. Another popular alternative approach followed by Embedded Engineers to build a Custom CPU /   Processor with the only required functionality thereby saving a large amount of the resources as compared to adding Microblaze instance. The course will discuss all the fundamentals required to build a simple processor/ CPU with Verilog HDL and strategies to test its functionality. After completing this course, you will understand all the necessary skills required to build Complex CPU architecture to meet requirements. Best wishes for crafting your own processor.

Course Curriculum

Chapter 1: Adding Arithmetic Unit

Lecture 1: Understanding Processor architecture

Lecture 2: Agenda

Lecture 3: Types of Instructions

Lecture 4: Addressing Modes

Lecture 5: Understanding Intruction Register

Lecture 6: Adding Instruction Register and GPR to Processor

Lecture 7: Understanding Arithmetic and Move intructions of Processor

Lecture 8: Adding MOV Instructions

Lecture 9: Adding Arithmetic Instructions

Lecture 10: Adding TB to verify Instructions P1

Lecture 11: Adding TB to verify Instructions P2

Lecture 12: Design Code

Lecture 13: Testbench Code

Lecture 14: OneNote Slides

Chapter 2: Adding Logical Unit

Lecture 1: Agenda

Lecture 2: Supported Logical Operations

Lecture 3: Adding Logical operations to RTL

Lecture 4: Adding TB to verify Logical Operations

Lecture 5: Analyzing RTL output

Lecture 6: Design Code

Lecture 7: Testbench Code

Lecture 8: OneNote Slides

Chapter 3: Adding Conditions Flags

Lecture 1: Agenda

Lecture 2: Condition flags usage

Lecture 3: Logic for Carry flag

Lecture 4: Logic for Sign, and Zero Flag

Lecture 5: Logic for Overflow flag

Lecture 6: Adding Sign flag to RTL

Lecture 7: Adding Carry flag to RTL

Lecture 8: Adding Zero flag to RTL

Lecture 9: Adding Overflow flag to RTL

Lecture 10: Verifying operation of condition flags

Lecture 11: Design Code

Lecture 12: Testbench Code

Lecture 13: OneNote Slide

Chapter 4: Adding Program and Data memory

Lecture 1: Agenda

Lecture 2: Processor architecture based on Memory model

Lecture 3: Working with Memory Generator IP

Lecture 4: Code

Lecture 5: COE File

Lecture 6: Working with Verilog arrays

Lecture 7: Code

Lecture 8: Adding Memory to Processor RTL P1

Lecture 9: Converting independent always block to tasks

Lecture 10: Adding logic to read Instructions from Program Memory after fixed delay

Lecture 11: Adding Instructions to work with Ports and Data Memory

Lecture 12: Program use for testing operation of RTL

Lecture 13: Adding TB to verify operation of RTL

Lecture 14: Design Code

Lecture 15: Testbench Code

Lecture 16: OneNote Slides

Chapter 5: Adding Jumping and Branching Instructions

Lecture 1: Agenda

Lecture 2: Branch and Jump Instructions our processor support

Lecture 3: Operation of Jump Instructions

Lecture 4: Adding Jump instructions to Processor RTL

Lecture 5: Modifying FSM to incorporate Jump, Branch and Halt : Flowchart

Lecture 6: Adding FSM to RTL

Lecture 7: Testing existing program with new FSM

Lecture 8: Code to Verify Jump and Branch Instructions

Lecture 9: Executing Testbench Code

Lecture 10: Design Code

Lecture 11: Testbench Code

Lecture 12: Program memory content

Lecture 13: OneNote Slides

Instructors

Kumar Khandagle
Trainer @ NAMASTE FPGA

Rating Distribution

1 stars: 1 votes

2 stars: 1 votes

3 stars: 11 votes

4 stars: 46 votes

5 stars: 76 votes

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